ESD Input protection using a floating gate neuron MOSFET as a tunable trigger element
First Claim
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1. A floating gate MOS transistor for triggering a silicon control rectifier into an "ON" state upon an electrostatic discharge at a node of a circuit to be protected without placing the MOS transistor into a breakdown state, the floating gate MOS transistor comprising:
- a source region of a predetermined conductivity type;
a drain region of the predetermined conductivity type;
a channel between the source and drain regions;
a floating gate disposed above and insulated from the channel region;
a first gate capacitively coupled to the floating gate with a capacitive coupling ratio of w1, the first gate being in electrical communication with the node via an electrical path that includes the drain region; and
a second gate electrically connected to the source region and capacitively coupled to the floating gate with a capacitive coupling ratio of W2 ;
wherein the capacitive coupling between the floating gate, first gate, and second gate fulfills the relationship
space="preserve" listing-type="equation">V.sub.fg =V.sub.1 w.sub.1 +V.sub.2 w.sub.2where Vfg is the potential at the floating gate, V1 is the potential at the first gate and V2 is the potential at the second gate;
whereby upon an electrostatic discharge of a predetermined discharge potential at the node, V1 is increased, due to the first gate'"'"'s electrical communication with the node, to a first gate potential that is sufficient to increase Vfg to a floating gate potential that turns on the floating gate MOS transistor, thereby triggering said silicon control rectifier into an "ON" state without placing the floating gate MOS transistor into a breakdown state.
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Abstract
Disclosed is a floating gate neuron MOS transistor that may be incorporated into devices such as low voltage silicon control rectifiers for protection of internal circuits against electrostatic discharge. The transistor includes two or more input gates capacitively coupled to the floating gate. By adjusting the coupling ratio of the input gates, it is possible to control the transistor drain turn-on voltage very precisely and thereby turn on the rectifier without relying on avalanche breakdown of the transistor.
15 Citations
9 Claims
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1. A floating gate MOS transistor for triggering a silicon control rectifier into an "ON" state upon an electrostatic discharge at a node of a circuit to be protected without placing the MOS transistor into a breakdown state, the floating gate MOS transistor comprising:
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a source region of a predetermined conductivity type; a drain region of the predetermined conductivity type; a channel between the source and drain regions; a floating gate disposed above and insulated from the channel region; a first gate capacitively coupled to the floating gate with a capacitive coupling ratio of w1, the first gate being in electrical communication with the node via an electrical path that includes the drain region; and a second gate electrically connected to the source region and capacitively coupled to the floating gate with a capacitive coupling ratio of W2 ; wherein the capacitive coupling between the floating gate, first gate, and second gate fulfills the relationship
space="preserve" listing-type="equation">V.sub.fg =V.sub.1 w.sub.1 +V.sub.2 w.sub.2where Vfg is the potential at the floating gate, V1 is the potential at the first gate and V2 is the potential at the second gate; whereby upon an electrostatic discharge of a predetermined discharge potential at the node, V1 is increased, due to the first gate'"'"'s electrical communication with the node, to a first gate potential that is sufficient to increase Vfg to a floating gate potential that turns on the floating gate MOS transistor, thereby triggering said silicon control rectifier into an "ON" state without placing the floating gate MOS transistor into a breakdown state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification
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Current AssigneeNational Semiconductor Corporation (Texas Instruments, Inc.)
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Original AssigneeNational Semiconductor Corporation (Texas Instruments, Inc.)
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InventorsChi, Min-hwa, Bergemont, Albert
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Primary Examiner(s)Thomas, Tom
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Assistant Examiner(s)Abraham, Fetsum
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Application NumberUS08/713,026Time in Patent Office1,202 DaysField of Search257/173-175, 257/355-360, 361/20, 361/90-92, 361/118, 361/126, 361/200, 361/272US Class Current257/175CPC Class CodesH01L 27/0262 including a PNP transistor ...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
