Vertical transistor and method

• US 6,008,519 A
• Filed: 12/15/1997
• Issued: 12/28/1999
• Est. Priority Date: 12/16/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Plumpton, Donald L., Kim, Tae S., Yang, Jau-Yuann, Yuan, Han-Tzong
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): VU, HUNG K
• Application Number:
  US08/990,549
• Time in Patent Office: 743 Days
• Field of Search: 257/60, 257/135, 257/136, 257/263, 257/264, 257/265, 257/266, 257/267, 257/302, 257/328, 257/329, 257/330, 257/331, 257/332, 257/333, 257/334, 257/279, 257/297, 438/173, 438/192, 438/193, 438/195
• US Class Current: 257/329
• CPC Class Codes: H01L 29/66416 Static induction transistors [SIT] with an active layer made of a group 13/15 material H01L29/66454
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT

Abstract

A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).

Claims

1. A vertical transistor, comprising:

a first semiconductor layer of a first conductive type;

a gate structure of a second conductive type disposed on the first semiconductor layer;

the gate structure including a plurality of gates separated by channels;

a second semiconductor layer of the first conductive type disposed over the gate structure and in the channels;

an arresting element disposed between an upper surface of the gate and the second semiconductor layer; and

a void formed in the second semiconductor layer over the gate.

2. The vertical transistor of claim 1, wherein:

the first conductive type is a n-type conductor; and

the second conductive type is a p-type conductor.

3. The vertical transistor of claim 1, wherein the first semiconductor layer is disposed on a substrate.

4. The vertical transistor of claim 1, the first semiconductor layer, the gate structure, and the second semiconductor layer further comprising III-V semiconductor material.

5. The vertical transistor of claim 1, the first semiconductor layer, the gate structure, and the second semiconductor layer further comprising gallium arsenide (GaAs).

6. The vertical transistor of claim 1, the arresting elements further comprising material selected from the group of silicon dioxide (SiO₂) and silicon nitride (Si₃ N₄).

7. The vertical transistor of claim 1, further comprising a low resistance element disposed between the arresting element and the upper surface of the gate.

8. The vertical transistor of claim 7, the low resistance elements further comprising tungsten silicon (W₅ Si₃).

9. The vertical transistor of claim 1, further comprising a metal element disposed between the arresting element and the upper surface of the gate.

10. The vertical transistor of claim 9, the metal elements further comprising tungsten silicon (W₅ Si₃).

11. An integrated circuit, comprising:

a substrate of a first conductive type;

a first source/drain layer of the first conductive type;

a gate structure of a second conductive type disposed on the first source/drain layer;

the gate structure including a plurality of gates separated by channels;

a second source/drain layer of the first conductive type disposed over the gate structure and in the channels;

an arresting element disposed between an upper surface of the gate and the second source/drain layer; and

a void formed in the second source/drain layer over the gate.

12. The integrated circuit of claim 11, wherein:

the first conductive type is an n-type conductor; and

the second conductive type is a p-type conductor.

13. The integrated circuit of claim 11, the first source/drain layer, the gate structure, and the second source/drain layer further comprising III-V semiconductor material.

14. The integrated circuit of claim 11, the first source/drain layer, the gate structure, and the second source/drain layer further comprising gallium arsenide (GaAs).

15. The integrated circuit of claim 11, the arresting elements further comprising material selected from the group of silicon dioxide (SiO₂) and silicon nitride (Si₃ N₄).