Integrated circuit employing simultaneously formed isolation and transistor trenches

• US 6,008,521 A
• Filed: 02/23/1998
• Issued: 12/28/1999
• Est. Priority Date: 10/08/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I.
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US09/027,573
• Time in Patent Office: 673 Days
• Field of Search: 257/327, 257/330, 257/333, 257/334, 257/510, 257/514, 257/374
• US Class Current: 257/330
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A semiconductor fabrication process in which a transistor trench and an isolation trench are simultaneously formed in a semiconductor substrate. The transistor trench is laterally displaced from the isolation trench. Thereafter the isolation trench is filled with an isolation material and a gate dielectric is formed on the floor of the transistor trench. Next, a conductive gate is formed on the gate dielectric and a source/drain impurity distribution is introduced into a source region and a drain region of the semiconductor substrate. The drain region and the source region are laterally disposed on either side of the transistor trench. In a presently preferred embodiment, the semiconductor substrate comprises a substantially single crystal p+ silicon bulk and a p- epitaxial layer formed upon the p+ silicon bulk. Preferably, the process of forming a transistor trench and the isolation trench includes depositing a photoresist layer on an upper surface of the semiconductor substrate, patterning the photoresist layer to expose an upper surface of an isolation trench region and an upper surface of a transistor trench region, anisotropically etching the isolation trench and the transistor trench region with a chlorinated plasma and stripping the photoresist layer. The process of filling the isolation trench with an isolation material preferably comprises depositing an isolation dielectric on the topography defined by the upper surface of the semiconductor substrate and the isolation trench and removing the isolation dielectric from regions exterior to the isolation trench.

Claims

1. An integrated circuit, comprising:

a semiconductor substrate, wherein said semiconductor substrate includes a first and a second active region laterally disposed on either side of an isolation structure and wherein said first and second active region each include a transistor trench extending downward a trench depth below an upper surface of said semiconductor substrate;

a first transistor formed within said first active region of said semiconductor substrate; and

a second transistor formed within said second active region of said semiconductor substrate, wherein said first and said second transistor each comprise;

a gate dielectric formed on a floor of said transistor trench such that said gate dielectric is vertically displaced a transistor trench depth below said upper surface of said semiconductor substrate;

a conductive gate in contact with said gate dielectric above a channel region of said semiconductor substrate wherein said channel region is vertically displaced below said trench floor extending laterally from a first sidewall of said transistor trench to a position intermediate between said first sidewall and a second sidewall of said transistor trench such that a lateral dimension of said channel region is less than a lateral dimension of said transistor trench;

a source/drain impurity distribution within a source region and a drain region of said semiconductor substrate, wherein said source region and said drain region are laterally disposed on either side of said transistor trench extending vertically from an upper surface of said semiconductor substrate to a depth approximately equal to said trench depth; and

a source side impurity distribution extending laterally from said source region to said channel region of said semiconductor substrate.

2. The integrated circuit of claim 1 wherein said source/drain impurity distribution of said first and second transistors comprise ions selected from the group consisting of phosphorous and arsenic, and further wherein a conductivity of said channel region is p-type such that said transistors each comprise an n-channel transistor.

3. The integrated circuit of claim 1 wherein said source/drain impurity distribution of said first and second transistors comprise boron ions, and further wherein a conductivity of said channel region is n-type such that said transistors each comprise a p-channel transistor.

4. The integrated circuit of claim 1 wherein said first transistor is an n-channel transistor and said second transistor is an p-channel transistor.

5. The integrated circuit of claim 1, wherein said source side impurity distribution comprises an impurity distribution of the same conductivity type as said source/drain impurity distribution.

6. The integrated circuit of claim 5, wherein said source side impurity distribution comprises a higher concentration of impurities than said source/drain impurity distribution.

7. The integrated circuit of claim 6, wherein said source side impurity distribution comprises a impurity concentration of greater than approximately 1×

10¹⁹ atoms/cm³.

8. The integrated circuit of claim 1, wherein said source region and said drain region both extend a junction depth below the trench depth.

9. The integrated circuit of claim 8, wherein said junction depth is less than approximately 0.2 microns.

10. An integrated circuit, comprising:

a transistor trench defined within an active region of a semiconductor substrate, wherein said transistor trench extends below an upper surface of said semiconductor substrate;

a transistor formed within said active region, the transistor comprising;

a gate dielectric arranged within said transistor trench;

a conductive gate arranged within the transistor trench and above said gate dielectric;

a channel region within the semiconductor substrate, wherein said channel region is vertically displaced below said conductive gate, and wherein said channel region extends laterally between a first sidewall of said transistor trench and a position intermediate between said first sidewall and a second sidewall of said transistor trench;

a source region and a drain region arranged within said semiconductor substrate on opposite sides of said transistor trench, wherein said source region and said drain region each vertically extend from an upper surface of said semiconductor substrate to a depth below said trench; and

a heavily doped impurity distribution arranged within said semiconductor substrate, wherein said heavily doped impurity region laterally extends from said second sidewall of the transistor trench to the channel region.

11. The integrated circuit of claim 10, wherein both said source region and said drain region comprise an impurity distribution, and wherein the impurity distribution within said source region is the same type as said impurity distribution within said drain region.

12. The integrated circuit of claim 10, The integrated circuit of claim 8, wherein said source region and said drain region extend a junction depth below said trench, and wherein said junction depth is less than approximately 0.2 microns.

13. The integrated circuit of claim 10, wherein said source region and said drain region both comprise a source/drain impurity distribution, and wherein the heavily doped impurity distribution comprises an impurity distribution of the same type as the source/drain impurity distribution, and wherein the heavily doped impurity distribution comprises a higher concentration of impurities than said source region or said drain region.

14. The integrated circuit of claim 13, wherein said heavily doped impurity distribution comprises a impurity concentration of greater than approximately 1×

10¹⁹ atoms/cm³.