Differential CMOS logic family

• US 6,008,670 A
• Filed: 08/19/1997
• Issued: 12/28/1999
• Est. Priority Date: 08/19/1997
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: HP Inc.
• Inventors: Duffner, Barbara J., Pace, Bradley D., Engelhard, Holger
• Primary Examiner(s): Santamauro, Jon
• Application Number:
  US08/914,195
• Time in Patent Office: 861 Days
• Field of Search: 326/17, 326/115, 326/112, 326/119, 326/121, 326/49-50, 327/407-408
• US Class Current: 326/115
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

Disclosed herein is a differential CMOS cell that achieves faster switching speeds than conventional CMOS logic by 1) biasing a differential pair of output nodes to a relatively high logic low voltage threshold, and 2) pulling up the differential pair of output nodes to a logic high voltage level. The differential CMOS cell is designed such that the difference between logic low and logic high voltage thresholds is much less than in traditional CMOS circuits (i.e., approximately 0.8 V-1.0 V as compared to 2.6 V). A lower voltage swing allows for fast switching of a differential output signal. In a preferred embodiment, the differential CMOS cell receives a primary differential input signal, and respective first and second secondary differential input signals. The differential CMOS cell includes a differential pair of arm circuits, each comprising a primary input switch for receiving a component of the primary differential input signal, and a differential pair of secondary input switches for receiving either the first or second secondary differential input signal. Each arm circuit is coupled between a current source and a voltage source. In operation, the primary differential input signal selects one of the first or second secondary differential input signals to be output as the differential output signal.

Claims

1. A CMOS circuit comprising:

at least three differential CMOS cells, each differential CMOS cell comprising;

first and second arm circuits connected in parallel between a current source and a voltage source;

wherein the first arm circuit comprises a first primary input switch, a first output node, a first resistive load, and first and second secondary input switches, the first primary input switch being coupled to the current source, the first resistive load being coupled between the first output node and the voltage source, the first secondary input switch being coupled between the first primary input switch and the first output node, and the second secondary input switch being coupled between the first primary input switch and a second output node; and

wherein the second arm circuit comprises a second primary input switch, the second output node, a second resistive load, and third and fourth secondary input switches, the second primary input switch being coupled to the current source, the second resistive load being coupled between the second output node and the voltage source, the third secondary input switch being coupled between the second primary input switch and the first output node, and the fourth secondary input switch being coupled between the second primary input switch and the second output node;

wherein the first and second output nodes of first and second differential CMOS cells are respectively connected to control inputs of the first, second, third, and fourth secondary input switches of a third differential CMOS cell;

whereby when a first differential select signal is received at control inputs of the primary input switches of the first and second differential CMOS cells, and a second differential select signal is received at control inputs of the primary input switches of the third differential CMOS cell, one of four differential signals received by the secondary input switches of the first and second differential CMOS cells is output at the first and second output nodes of the third differential CMOS cell.

2. A differential CMOS cell, comprising:

first and second arm circuits connected in parallel between a current source and a voltage source;

wherein the first arm circuit comprises a first primary input switch, a first output node, a first resistive load, and first and second secondary input switches, the first primary input switch being coupled to the current source, the first resistive load being coupled between the first output node and the voltage source, the first secondary input switch being coupled between the first primary input switch and the first output node and having a control input tied to a logic low, and the second secondary input switch being coupled between the first primary input switch and a second output node and having a control input tied to a logic high; and

wherein the second arm circuit comprises a second primary input switch, the second output node, a second resistive load, and third and fourth secondary input switches, the second primary input switch being coupled to the current source, the second resistive load being coupled between the second output node and the voltage source, the third secondary input switch being coupled between the second primary input switch and the first output node, and the fourth secondary input switch being coupled between the second primary input switch and the second output node;

whereby when complementary components of a first differential logic signal are respectively received at control inputs of the third and fourth secondary input switches, and complementary components of a second differential logic signal are respectively received at control inputs of the first and second primary input switches, the differential output signal produced by the first differential CMOS cell represents a logical AND of the first and second differential logic signals.

3. A differential CMOS cell, comprising:

first and second arm circuits connected in parallel between a current source and a voltage source;

wherein the first arm circuit comprises a first primary input switch, a first output node, a first resistive load, and first and second secondary input switches, the first primary input switch being coupled to the current source, the first resistive load being coupled between the first output node and the voltage source, the first secondary input switch being coupled between the first primary input switch and the first output node, and the second secondary input switch being coupled between the first primary input switch and a second output node; and

wherein the second arm circuit comprises a second primary input switch, the second output node, a second resistive load. and third and fourth secondary input switches, the second primary input switch being coupled to the current source, the second resistive load being coupled between the second output node and the voltage source, the third secondary input switch being coupled between the second primary input switch and the first output node and having a control input tied to a logic high, and the fourth secondary input switch being coupled between the second primary input switch and the second output node and having a control input tied to a logic low;

whereby when complementary components of a first differential logic signal are respectively received at control inputs of the first and second secondary input switches, and complementary components of a second differential logic signal are respectively received at control inputs of the first and second primary input switches, the differential output signal produced by the first differential CMOS cell represents a logical OR of the first and second differential logic signals.

4. A CMOS circuit, comprising:

at least two differential CMOS cells, each differential CMOS cell comprising;

first and second arm circuits connected in parallel between a current source and a voltage source;

wherein the first arm circuit comprises a first primary input switch, a first output node, a first resistive load, and first and second secondary input switches, the first primary input switch being coupled to the current source, the first resistive load being coupled between the first output node and the voltage source, the first secondary input switch being coupled between the first primary input switch and the first output node, and the second secondary input switch being coupled between the first primary input switch and a second output node;

wherein the second arm circuit comprises a second primary input switch, the second output node, a second resistive load, and third and fourth secondary input switches, the second primary input switch being coupled to the current source, the second resistive load being coupled between the second output node and the voltage source, the third secondary input switch being coupled between the second primary input switch and the first output node, and the fourth secondary input switch being coupled between the second primary input switch and the second output node;

wherein a control input of the first secondary input switch of a first differential CMOS cells is connected to the first output node of the first differential CMOS cell;

wherein a control input of the second secondary input switch of the first differential CMOS cell is connected to the second output node of the first differential CMOS cell;

wherein a control input of the first secondary input switch of a second differential CMOS cell is connected to the first output node of the second differential CMOS cell;

wherein a control input of the second secondary input switch of the second differential CMOS cell is connected to the second output node of the second differential CMOS cell; and

wherein the first and second output nodes of the first differential CMOS cell are respectively connected to the third and fourth secondary input switches of the second differential CMOS cell;

whereby when a differential clock signal is received at control inputs of the primary input switches of the first differential CMOS cell, an inversion of the differential clock signal is received at control inputs of the primary input switches of the second differential CMOS cell, and complementary components of a first differential logic signal are respectively received at control inputs of the third and fourth secondary switches of the first differential CMOS cell, the first and second differential CMOS cells function as a D type flip-flop.

5. A CMOS circuit as in claim 4, wherein:

a third differential CMOS cell is configured such that;

control inputs of the first and fourth secondary input switches are connected to one another to form input Ap; and

control inputs of the second and third secondary input switches are connected to one another to form input An;

the first and second output nodes of the third differential CMOS cell are respectively connected to the control inputs of the third and fourth secondary input switches of the first differential CMOS cell;

the first secondary input switch of the third differential CMOS cell is connected to the first output node of the second differential CMOS cell; and

the second secondary input switch of the third differential CMOS cell is connected to the second output node of the second differential CMOS cell;

whereby when the differential clock signal is received at control inputs of the primary input switches of the first differential CMOS cell, the inversion of the differential clock signal is received at control inputs of the primary input switches of the second differential CMOS cell, and a second differential logic signal is received at the primary inputs of the third differential CMOS cell, the first, second, and third differential CMOS cells function as a T type flip-flop.