High speed, low power, current mode comparator

• US 6,008,673 A
• Filed: 03/04/1999
• Issued: 12/28/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McDaniel, Bart R., Glass, Kevin W., Khalil, Waleed
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/265,217
• Time in Patent Office: 299 Days
• Field of Search: 327/55, 327/57, 327/65, 327/66, 327/67, 327/77, 327/88, 327/89, 327/103, 327/165
• US Class Current: 327/77
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03K 5/249 using clock signals
• CPC Class Codes: H03M 1/366 using current mode circuits, i.e. circuits in which the information is represented by current values rather than by voltage values

Abstract

A current regenerative comparator. A pair of cross coupled inverters are coupled to an equalizing transistor, an input current mirror and a reference current mirror, such that current flowing in the input current mirror is compared to the current flowing in the reference current mirror.

Claims

1. An apparatus comprising:

a pair of cross-coupled inverters;

an equalizing transistor coupled between a first source of a first n-transistor of a first inverter and a second source of a second n-transistor of a second inverter;

the equalizing transistor, an input current mirror and a reference current mirror coupled to the pair of cross-coupled inverters wherein the current flow in the input current mirror is compared to the current flow in the reference current mirror in response to an enable signal.

2. The apparatus of claim 1 further comprising:

a first transfer gate coupling an input node of the input current mirror to a gate node of the second inverter; and

a second transfer gate coupling an input node of the reference current mirror to a gate node of the first inverter, wherein both the first and second transfer gates are active when the enable signal is deasserted.

3. The apparatus of claim 1 further comprising:

a first isolation transistor isolating a positive power supply from the inverters when the enable signal is deasserted; and

a second isolation transistor isolating a negative power supply from the inverters when the enable signal is deasserted.

4. The apparatus of claim 1 wherein the inverters are of the push-pull variety built according a CMOS fabrication process.

5. A circuit comprising:

a pair of cross-coupled inverters having complimentary outputs indicative of a comparison of two input currents;

equalizing means for equalizing a voltage at a first output node of a first transistor of a first inverter and a second output node of a second transistor of a second inverter in response to an enable signal being deasserted; and

a first current mirror and a second current mirror coupled to the first output node and the second output node, respectively, to reflect the input currents into the inverters.

6. The circuit of claim 5 further comprising:

nudging means for nudging the complimentary outputs in a direction which corresponds to a stable state of the comparison prior to the enable signal being asserted.

7. The circuit of claim 5 further comprising:

power reduction means for reducing a power consumption of the circuit when the enable signal is deasserted.