Continuously adjustable delay-locked loop
First Claim
1. A continuously adjustable delay-lock loop circuit, the circuit comprising:
- a first variable delay path circuit having inputs to receive a clock signal and a delay control signal, for controllably delaying the clock signal by a first variable time interval that is inversely related to the delay control signal, in order to generate a first delayed clock signal;
a second variable delay path circuit having inputs to receive the clock signal and the delay control signal, wherein the second variable delay path is operable to delay the clock signal by a second variable time interval that is directly related to the delay control signal in order to generate a second delayed clock signal;
a path selector for selecting one at a time of the first and second delayed clock signals for output as a recovered clock signal; and
a path selector circuit arranged so as to toggle between a first state selecting the first delayed clock signal as the recovered clock signal, and a second state selecting the second delayed clock signal as the recovered clock signal, when the first and second delayed clock signals are offset from each other by at least a predetermined phase difference approximately equal to one bit unit interval, thereby minimizing any discontinuity in the recovered clock signal.
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Abstract
A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.
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Citations
12 Claims
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1. A continuously adjustable delay-lock loop circuit, the circuit comprising:
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a first variable delay path circuit having inputs to receive a clock signal and a delay control signal, for controllably delaying the clock signal by a first variable time interval that is inversely related to the delay control signal, in order to generate a first delayed clock signal; a second variable delay path circuit having inputs to receive the clock signal and the delay control signal, wherein the second variable delay path is operable to delay the clock signal by a second variable time interval that is directly related to the delay control signal in order to generate a second delayed clock signal; a path selector for selecting one at a time of the first and second delayed clock signals for output as a recovered clock signal; and a path selector circuit arranged so as to toggle between a first state selecting the first delayed clock signal as the recovered clock signal, and a second state selecting the second delayed clock signal as the recovered clock signal, when the first and second delayed clock signals are offset from each other by at least a predetermined phase difference approximately equal to one bit unit interval, thereby minimizing any discontinuity in the recovered clock signal.
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2. A continuously adjustable delay circuit comprising:
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a first adjustable means for delaying a master clock input signal responsive to a delay control signal to form a first delayed clock signal; a second adjustable means for delaying the master clock input signal responsive to the delay control signal to form a second delayed clock signal; and means for selecting one at a time of the first and second delayed clock signals for output as a recovered clock signal, wherein the selecting means includes means for switching the selection as between the first and second delayed clock signals when the first and second delayed clock signals are substantially in phase with each other, thereby minimizing discontinuity in the recovered clock signal. - View Dependent Claims (3)
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4. A continuously variable delay circuit, the circuit comprising:
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a first delay circuit having input and output terminals and a control terminal, the input terminal of the first delay circuit being configured to receive a reference signal and wherein the first delay circuit is operable to delay the reference signal in direct relation to a tune signal received at the control terminal of the first delay circuit; a second delay circuit having input and output terminals and a control terminal, the input terminal of the second delay circuit being configured to receive the reference signal and wherein the second delay circuit is operable to delay the reference signal in inverse relation to the tune signal received at the control terminal of the second delay circuit; a path selection circuit having first and second input terminals and an output terminal, wherein the first input terminal of the path selection circuit is coupled to the output terminal of the first delay circuit and the second input terminal of the path selection circuit is coupled to the output terminal of the second delay circuit, the path selection circuit being operable to generate a selection signal at the output terminal of the path selection circuit, wherein the selection signal selects between the first and second delay circuits responsive to the delayed reference signal at the output terminal of the first delay circuit being in phase with the delayed reference signal at the output terminal of the second delay circuit; and a first multiplexor having first and second input terminals, a control terminal and an output terminal, wherein the first input terminal of the first multiplexor is coupled to the output terminal of the first delay circuit, the second input terminal of the first multiplexor is coupled to the output terminal of the second delay circuit and the control terminal of the first multiplexor is coupled to the output terminal of the path selection circuit. - View Dependent Claims (5, 6, 7, 8)
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9. A continuously variable delay circuit, the circuit comprising:
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a first delay circuit having input and output terminals and a control terminal, the input terminal of the first delay circuit being configured to receive a reference signal and wherein the first delay circuit is operable to delay the reference signal in direct relation to a tune signal received at the control terminal of the first delay circuit; a second delay circuit having input and output terminals and a control terminal, the input terminal of the second delay circuit being configured to receive the reference signal and wherein the second delay circuit is operable to delay the reference signal in inverse proportion to the tune signal received at the control terminal of the second delay circuit; a path selection circuit having first, second and third input terminals and an output terminal, wherein the first input terminal of the path selection circuit is coupled to the output terminal of the first delay circuit and the second input terminal of the path selection circuit is coupled to the output terminal of the second delay circuit, the path selection circuit being operable to generate a selection signal at the output terminal of the path selection circuit; and a first multiplexor having first and second input terminals, a control terminal and an output terminal, wherein the first input terminal of the first multiplexor is coupled to the output terminal of the first delay circuit, the second input terminal of the first multiplexor is coupled to the output terminal of the second delay circuit and the control terminal of the first multiplexor is coupled to the output terminal of the path selection circuit and further wherein the output terminal of the first multiplexor is coupled to the third input terminal of the path selection circuit. - View Dependent Claims (10, 11, 12)
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Specification