Digital compensation for wideband modulation of a phase locked loop frequency synthesizer

• US 6,008,703 A
• Filed: 01/31/1997
• Issued: 12/28/1999
• Est. Priority Date: 01/31/1997
• Status: Expired due to Term

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Chandrakasan, Anantha P., Perrott, Michael H., Sodini, Charles G.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US08/791,215
• Time in Patent Office: 1,061 Days
• Field of Search: 332/100-102, 331/16, 331/18, 331/23, 331/25, 375/303-307, 375/376
• US Class Current: 332/100
• CPC Class Codes: H03C 3/0925 applying frequency modulation at the divider in the feedback loop
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H03L 7/1978 using a cycle or pulse removing circuit
• CPC Class Codes: H04L 25/03834 using pulse shaping
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/2017 in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation H04L27/201 takes precedence

Abstract

A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency. This digital processor is connected to the phase locked loop frequency divider to modulate the divider based on the digitally-processed input modulation data, whereby a voltage controlled oscillator of the phase locked loop is controlled to produce a modulated output carrier signal having a modulation bandwidth that exceeds the phase locked loop cutoff frequency. The digital processing of the modulation data can be implemented by adapting a digital FIR Gaussian transmit filter such that its filter characteristic reflects the intended modulation data amplification as well as enables Gaussian Frequency Shift Keyed modulation. With this implementation, no additional componentry beyond the PLL system is needed to implement the digital modulation data processing provided by the invention.

Claims

1. Apparatus for modulating a phase locked loop, the phase locked loop comprising a voltage controlled oscillator responsive to a control signal for generating an output carrier signal that is modulated by input modulation data and that has a controlled frequency;

a reference frequency signal source;

a phase comparator connected to receive a reference frequency signal and the modulated output carrier signal for generating a difference signal;

a low pass loop filter connected to filter the difference signal for producing the voltage controlled oscillator control signal; and

frequency divider means connected between the voltage controlled oscillator output and the phase comparator for dividing the output carrier signal frequency;

the phase locked loop being characterized by a frequency response having a characteristic cutoff frequency;

the apparatus comprising;

means for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency of the phase locked loop frequency response; and

means coupled to the modulation data receiving means for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency, and connected to the phase locked loop frequency divider means to modulate the divider means based on the digitally-processed input modulation data, whereby the voltage controlled oscillator is controlled to produce a modulated output carrier signal having a modulation bandwidth that exceeds the phase locked loop cutoff frequency.

2. The apparatus of claim 1 wherein the means for digitally processing the input modulation data is adapted to amplify the input modulation data, at frequencies higher than the phase locked loop cutoff frequency, by a selected gain factor that corresponds to an attenuation factor characteristic of the phase locked loop frequency response at frequencies higher than the phase locked loop cutoff frequency.

3. The apparatus of claim 2 wherein the phase locked loop frequency response attenuation factor to which the digital processing gain factor corresponds is based on a dominant pole in the phase locked loop frequency response.

4. The apparatus of claim 3 wherein the first-order pole in the phase locked loop frequency response to which the digital processing gain factor corresponds is produced by a dominant pole in the low pass loop filter.

5. The apparatus of claim 1 wherein the phase locked loop frequency response cutoff frequency is less than about 1.0 MHz and wherein the carrier signal modulation bandwidth is greater than about 1.0 MHz.

6. The apparatus of claim 2 wherein the means for digitally processing the input modulation data comprises digital finite impulse response compensation filter means having a compensation frequency response characterized by the selected gain factor at frequencies higher than the phase locked loop cutoff frequency.

7. The apparatus of claim 6 wherein the digital finite impulse response compensation filter means comprises a digital read-only-memory circuit having a stored look-up-table for mapping a given digital modulation data sample input to the circuit to a corresponding filtered output digital modulation data value based on a convolution of the given digital modulation data sample with the digital finite impulse compensation frequency response.

8. The apparatus of claim 6 wherein the means for digitally processing the input modulation data further comprises a digital finite impulse response Gaussian filter means having a Gaussian frequency response characterized by a cutoff frequency that corresponds to the digital modulation data bandwidth, for filtering the digital input modulation data to enable Gaussian-Frequency-Shift-Keyed modulation of the voltage controlled oscillator output carrier signal.

9. The apparatus of claim 6 wherein the digital finite impulse response compensation filter means is adapted to have a compensated Gaussian frequency response corresponding to a convolution of the compensation frequency response with a Gaussian frequency response characterized by a cutoff frequency that corresponds to the digital modulation data bandwidth, for filtering the digital input modulation data to enable Gaussian-Frequency-Shift-Keyed modulation of the voltage controlled oscillator output carrier signal.

10. The apparatus of claim 9 wherein the digital finite impulse response compensated Gaussian filter means comprises a digital read-only-memory circuit having a stored look-up-table for mapping a given digital modulation data sample input to the circuit to a corresponding filtered output digital modulation data value based on a convolution of the given digital modulation data sample with the digital finite impulse compensated Gaussian frequency response.

11. The apparatus of claim 1 wherein the phase locked loop frequency divider means comprises a multi-modulus frequency divider connected to receive the digitally-processed digital input modulation data for modulating the divider modulus.

12. The apparatus of claim 11 wherein the multi-modulus frequency divider comprises a fractional-N synthesizer, where N is the frequency divider modulus.

13. The apparatus of claim 12 wherein the fractional-N synthesizer comprises a digital Σ

-Δ

modulator connected to receive the digitally-processed digital input modulation data for producing a modulated digital modulus control signal, the multi-modulus divider connected to receive the control signal for controlling the divider modulus.

14. The apparatus of claim 13 wherein the digital Σ

-Δ

modulator comprises a cascade of digital Σ

-Δ

modulator loops, each loop of an order, L, that is less than an order, M, of the cascade of loops together, the cascade producing the modulated digital modulus control signal.

15. The apparatus of claim 14 wherein the cascade of digital Σ

-Δ

modulator loops comprises a pipelined cascade of digital Σ

-Δ

modulator loops, each cascaded loop including a delay means for accommodating pipelining of the production of the modulated digital modulus control signal.

16. The apparatus of claim 4 wherein the low pass loop filter comprises an analog filter circuit having a characteristic RC time constant that produces the first-order pole in the phase locked loop frequency response.

17. The apparatus of claim 16 wherein the analog filter circuit comprises a switched-capacitor network for producing the low pass filter RC time constant.

18. The apparatus of claim 2 further comprising an open loop gain controller connected to the low pass loop filter for adjusting open loop gain of the phase locked loop to obtain a prespecified phase locked loop frequency response.

19. Apparatus for modulating a phase locked loop, the phase locked loop comprising a voltage controlled oscillator responsive to a control signal for generating an output carrier signal that is modulated by input modulation data and that has a controlled frequency;

a reference frequency signal source;

a phase comparator connected to receive a reference frequency signal and the modulated output carrier signal for generating a difference signal;

a low pass loop filter connected to filter the difference signal for producing the voltage controlled oscillator control signal; and

frequency divider means connected between the voltage controlled oscillator output and the phase comparator for dividing the output carrier signal frequency;

the phase locked loop being characterized by a frequency response having a characteristic cutoff frequency;

the apparatus comprising;

means for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency of the phase locked loop frequency response; and

digital filter means connected to receive the digital input modulation data for digitally filtering the input modulation data based on a Gaussian finite impulse frequency response with a cutoff frequency corresponding to the digital modulation data bandwidth and a gain characteristic for amplifying modulation data at frequencies higher than the phase locked loop cutoff frequency, the digital filter means connected to the phase locked loop frequency divider means to modulate the divider means based on the digitally-filtered input modulation data, whereby the voltage controlled oscillator is controlled to produce Gaussian Frequency Shift Keyed modulation of the output carrier signal with a modulation bandwidth that exceeds the phase locked loop cutoff frequency.

20. A phase locked loop frequency synthesizer, characterized by a frequency response having a characteristic cutoff frequency, for modulating a carrier signal having a controllable carrier signal frequency, the phase locked loop comprising:

a voltage controlled oscillator responsive to a control signal for generating an output carrier signal that is modulated by input modulation data and that has a controlled frequency;

a reference frequency signal source;

a phase comparator connected to receive a reference frequency signal from the reference frequency signal source and for receiving the modulated output carrier signal for generating a difference signal;

a low pass loop filter connected to filter the difference signal for producing the voltage controlled oscillator control signal;

frequency divider means connected between the voltage controlled oscillator output and the phase comparator for dividing the output carrier signal frequency;

means for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency of the phase locked loop frequency response; and

Gaussian transmit filter means coupled to the modulation data receiving means for digitally processing the digital input modulation data to apply a Gaussian finite impulse response to the digital input modulation data and to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency, the Gaussian transmit filter means connected to the phase locked loop frequency divider means to modulate the divider means based on the digitally-processed input modulation data, whereby the voltage controlled oscillator is controlled to enable Gaussian Frequency Shift Keyed modulation of the output carrier signal, the carrier signal modulation bandwidth exceeding the phase locked loop cutoff frequency.

21. A method for modulating a phase locked loop, the phase locked loop comprising a voltage controlled oscillator responsive to a control signal for generating an output carrier signal that is modulated by input modulation data and that has a controlled frequency;

a reference frequency signal source;

a phase comparator connected to receive a reference frequency signal and the modulated output carrier signal for generating a difference signal;

a low pass loop filter connected to filter the difference signal for producing the voltage controlled oscillator control signal; and

frequency divider means connected between the voltage controlled oscillator output and the phase comparator for dividing the output carrier signal frequency;

the phase locked loop being characterized by a frequency response having a characteristic cutoff frequency;

the method comprising the steps of;

receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency of the phase locked loop frequency response;

digitally processing the digital input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency; and

modulating the phase locked loop divider means based on the digitally-processed digital input modulation data, whereby the voltage controlled oscillator is controlled to produce a modulated output carrier signal having a modulation bandwidth that exceeds the phase locked loop cutoff frequency.

22. The method of claim 21 wherein the step of digitally processing the digital input modulation data comprises a step of digitally filtering the digital input modulation data based on a digital finite impulse compensation frequency response characterized by a selected gain factor, at frequencies higher than the phase locked loop cutoff frequency, that corresponds to an attenuation factor characteristic of the phase locked loop frequency response at frequencies higher than the phase locked loop cutoff frequency.

23. The method of claim 22 wherein the step of digitally filtering the digital input modulation data comprises a step of Gaussian digital filtering of the input modulation data based on a digital finite impulse Gaussian compensation frequency response corresponding to a convolution of the compensation frequency response and a Gaussian frequency response characterized by a cutoff frequency that corresponds to the digital modulation data bandwidth, to enable Gaussian-Frequency-Shift-Keyed modulation of the voltage controlled oscillator output carrier signal.

24. Apparatus for modulating a phase locked loop, the phase locked loop comprising a voltage controlled oscillator responsive to a control signal for generating an output carrier signal that is modulated by input modulation data and that has a controlled frequency;

a reference frequency signal source;

a phase comparator connected to receive a reference frequency signal and the modulated output carrier signal for generating a difference signal;

a low pass loop filter connected to filter the difference signal for producing the voltage controlled oscillator control signal; and

frequency divider means connected between the voltage controlled oscillator output and the phase comparator for dividing the output carrier signal frequency;

the phase locked loop being characterized by a frequency response having a characteristic cutoff frequency;

the apparatus comprising;

means for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency of the phase locked loop frequency response; and

digital filter means connected to receive the digital input modulation data for digital filtering of the input modulation data based on a gain characteristic defined to compensate for low pass loop filter attenuation of input modulation data at frequencies higher than the phase locked loop cutoff frequency, the digital filter means connected to the phase locked loop frequency divider means to modulate the divider means based on the digitally-filtered input modulation data.

25. A phase locked loop frequency synthesizer, characterized by a frequency response having a characteristic cutoff frequency, for modulating a carrier signal having a controllable carrier signal frequency, the phase locked loop comprising:

a voltage controlled oscillator responsive to a control signal for generating an output carrier signal that is modulated by input modulation data and that has a controlled frequency;

a reference frequency signal source;

a phase comparator connected to receive a reference frequency signal from the reference frequency signal source and for receiving the modulated output carrier signal for generating a difference signal;

a low pass loop filter connected to filter the difference signal for producing the voltage controlled oscillator control signal;

frequency divider means connected between the voltage controlled oscillator output and the phase comparator for dividing the output carrier signal frequency;

means for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency of the phase locked loop frequency response; and

digital filter means coupled to the modulation data receiving means for digital filtering of the input modulation data based on a gain characteristic defined to compensate for low pass loop filter attenuation of input modulation data at frequencies higher than the phase locked loop cutoff frequency, the digital filter means connected to the phase locked loop frequency divider means to modulate the divider means based on the digitally-filtered input modulation data.