Operating a power electronic circuit arrangement having multiple power converters

• US 6,009,002 A
• Filed: 05/04/1998
• Issued: 12/28/1999
• Est. Priority Date: 05/17/1997
• Status: Expired due to Fees

• Current Assignee: Asea Brown Boveri AG (ABB Limited)
• Original Assignee: Asea Brown Boveri AG (ABB Limited)
• Inventors: Steimer, Peter
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US09/071,038
• Time in Patent Office: 603 Days
• Field of Search: 363/34, 363/37, 363/39, 363/40, 363/41, 363/65, 363/71
• US Class Current: 363/34
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 5/4585 having a rectifier with controlled elements
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters

Abstract

A method for operating a power electronic circuit having a first power convertor and at least one second power convertor is specified. The pulse duration-modulated driving of the switches of the circuit arrangement is effected according to a comparison of a reference oscillation with a carrier oscillation. According to the invention, a component of a third harmonic is admixed with the reference oscillation over virtually the entire drive-level range, in particular including low drive-level rates in the range from 20% to approximately 87%. It is also possible to admix a corresponding component of a ninth harmonic in the drive-level range from 20% to approximately 33%. This results in a low clock frequency for the first power convertor and the second power convertor need not have a feedback capability. (FIG. 1)

Claims

1. A power electronic circuit arrangement comprising:

a first power convertor which is connected to a power supply system via a first DC voltage intermediate circuit having a first intermediate circuit voltage and a first rectifier and which has one load terminal per phase;

at least one second power convertor having a second DC voltage intermediate circuit having a second intermediate circuit voltage, which second power convertor is connected to the load terminal of the first power convertor;

the first and second power convertors having switches which are driven with pulse duration modulation according to a comparison of an essentially sinusoidal reference oscillation with at least one carrier oscillation, in such a way that the second intermediate circuit voltage can be added to or subtracted from the first intermediate circuit voltage and a mapping of the reference oscillation is produced at the output of the power electronic circuit;

wherein

a component of a third harmonic is admixed with the reference oscillation over virtually the entire drive-level range of the power electronic circuit arrangement, in particular including a drive level of more than approximately 20% and less than approximately 87%.

2. The power electronic circuit arrangement as claimed in claim 1, wherein the amplitude of the admixed third harmonic is chosen such that a sum of the fundamental and the third harmonic never exceeds a maximum permitted value of the reference oscillation.

3. The power electronic circuit arrangement as claimed in claim 2, wherein the amplitude a₃ of the third harmonic is chosen according to the drive level as follows:

a₃ =-A_max +(A_max +a_3N)·

f₁, wherein

A_max =1 p.u. (maximum permitted value of the reference voltage)

a_3N =component of the 3rd harmonic which is admixed at f₁ =f_1N (nominal frequency)=1 p.u.

4. The power electronic circuit arrangement as claimed in claim 2, wherein a ninth harmonic having an amplitude a₉ according to the following relationship:

a₉ =-A_max +(A_max +a_3N)·

f₁, wherein p1 A_max =1 p.u. (maximum permitted value of the reference voltage) and

a_3N =component of the 3^rd harmonic which is admixed at f₁ =f_1N (nominal frequency)=1 p.u.

is admixed instead of the third harmonic starting from a drive level of approximately 33%.

5. The power electronic circuit arrangement as claimed in claim 1, wherein the first power convertor is constructed after the manner of a two-point invertor and the second power convertor is constructed after the manner of a two- or three-point invertor.

6. The power electronic circuit arrangement as claimed in claim 1, wherein the first power convertor is constructed after the manner of a three-point invertor and the second power convertor is constructed after the manner of a two- or three-point invertor.

7. A method for operating a power electronic circuit arrangement, the power electronic circuit arrangement comprising:

a first power convertor having switches and one load terminal per phase, the first power convertor being connected to a power supply system via a first rectifier and a first DC voltage intermediate circuit having a first intermediate circuit voltage;

at least one second power convertor having switches and a second DC voltage intermediate circuit that has a second intermediate circuit voltage, the at least one second power convertor being connected to the load terminal of the first power convertor; and

the method comprising the steps of;

driving the switches of the first and second power convertors with pulse duration modulation based on a comparison of an essentially sinusoidal reference oscillation with at least one carrier oscillation, in such a way that the second intermediate circuit voltage can be added to or subtracted from the first intermediate circuit voltage and a mapping of the reference oscillation is produced at the output of the power electronic circuit; and

admixing a component of a third harmonic with the reference oscillation over virtually an entire drive-level range of the power electronic circuit arrangement.

8. The method of claim 7, wherein:

the first power convertor is a polyphase power convertor; and

the range of the power electronic circuit arrangement over which the component of the third harmonic is admixed with the reference oscillation includes a drive level of more than approximately 20% and less than approximately 87%.

9. The method of claim 7, further comprising the step of choosing an amplitude of the third harmonic such that a sum of the fundamental and the third harmonic never exceeds a maximum permitted value of the reference oscillation.

10. The method of claim 9, wherein the amplitude a₃ of the third harmonic is chosen according to the drive level as follows:

a₃ =-A_max +(A_max +a_3N)·

f₁, wherein

A_max =1 p.u. (maximum permitted value of the reference voltage)

a_3N =component of the 3^rd harmonic which is admixed at f₁ =f_1N (nominal frequency)=1 p.u.

11. The method of claim 9, further comprising the step of admixing a ninth harmonic instead of the third harmonic starting from a drive level of approximately 33%, where the ninth harmonic has an amplitude a₉ according to the relationship:

a₉ =-A_max +(A_max +a_3N)·

f₁, wherein

A_max =1 p.u. (maximum permitted value of the reference voltage) and

a_3N =component of the 3^rd harmonic which is admixed at f₁ =f_1N (nominal frequency)=1 p.u.

12. The method of claim 7, wherein the first power convertor is constructed after the manner of a two-point invertor and the second power convertor is constructed after the manner of a two- or three-point invertor.

13. The method of claim 7, wherein the first power convertor is constructed after the manner of a three-point invertor and the second power convertor is constructed after the manner of a two- or three-point invertor.

14. A method for operating a power electronic circuit arrangement, comprising the steps of:

driving switches of first and second power convertors in the power electronic circuit arrangement with pulse duration modulation based on a comparison of an essentially sinusoidal reference oscillation with at least one carrier oscillation, to a) allow a second intermediate voltage input to the second power convertor to be added to or subtracted from a first intermediate voltage input to the first power convertor and b) produce a mapping of the reference oscillation at an output of the power electronic circuit; and

admixing a component of a harmonic with the reference oscillation over virtually an entire drive-level range of the power electronic circuit arrangement.

15. The method of claim 14, wherein the harmonic is a third harmonic.

16. The method of claim 15, wherein:

the first power convertor is a polyphase power convertor; and

the range of the power electronic circuit arrangement over which the component of the third harmonic is admixed with the reference oscillation includes a drive level of more than approximately 20% and less than approximately 87%.

17. The method of claim 15, further comprising the step of choosing an amplitude of the third harmonic such that a sum of the fundamental and the harmonic never exceeds a maximum permitted value of the reference oscillation.

18. The method of claim 15, wherein the amplitude a₃ of the third harmonic is chosen according to the drive level as follows:

a₃ =-A_max +(A_max +a_3N)·

f₁, wherein

A_max =1 p.u. (maximum permitted value of the reference voltage)

a_3N =component of the 3^rd harmonic which is admixed at f₁ =f_1N (nominal frequency)=1 p.u.

19. The method of claim 14, further comprising the step of admixing the harmonic starting from a drive level of approximately 33%, wherein the harmonic is a ninth harmonic having an amplitude a₉ according to the relationship:

a₉ =-A_max +(A_max +a_3N)·

f₁, wherein

A_max =1 p.u. (maximum permitted value of the reference voltage) and

a_3N =component of the 3^rd harmonic which is admixed at f₁ =f_1N (nominal frequency)=1 p.u.