Pulse-density-modulated controller with dynamic sequence

• US 6,009,007 A
• Filed: 02/12/1998
• Issued: 12/28/1999
• Est. Priority Date: 02/12/1998
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Pan, Tsung-Ming
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US09/022,495
• Time in Patent Office: 684 Days
• Field of Search: 363/17, 363/98, 363/132, 323/235, 323/238, 323/319, 323/321
• US Class Current: 363/98
• CPC Class Codes: H02M 7/53871 with automatic control of output voltage or current

Abstract

Apparatus for controlling pulse density is disclosed herein. The aforementioned apparatus including the following devices: A comparator that is used to compare an input reference voltage and a feedback voltage signal. A math processing device that is used to add the difference between the feedback voltage signal and an analog duty command signal to the analog duty command signal. A shift register that is used to generate a shift timing signal. A weighted averaging device that is used to carry out the operation of the weighted averaging of the feedback voltage signal according to the shift timing signal. A sequential switching device that is used to generate a switch-timing control signal by decoding the feedback voltage signal. A rectifying device that is used to output power with zero-current-switching. The rectifying means is driven by the switch-timing control signal.

Claims

1. Apparatus for controlling pulse density, said apparatus comprising:

a comparator for comparing an input reference voltage and a feedback voltage signal, said feedback signal being encoded;

math processing means for adding the difference between said feedback signal and an analog duty command signal to said analog duty command signal;

a shift register for generating a shift timing signal;

weighted averaging means for weighted averaging said feedback signal according to said shift timing signal;

sequential switching means for generating a switch-timing control signal by decoding said feedback voltage signal; and

rectifying means for outputting power with zero-current-switching, said rectifying means being driven by said switch-timing control signal.

2. The apparatus as claim 1, wherein said weighted averaging means averaging a sixteen bit digital pulse sequence.

3. The apparatus as claim 1, wherein said sequential switching means is a decoding circuit, said decoding circuit generates said switch-timing control signal by decoding said sixteen bit digital pulse train signal, said switch-timing control signal is a four bit digital signal.

4. The apparatus as claim 1, wherein said math processor is an adder, said adder comprises a buffer and two resistors.

5. The apparatus as claim 1, wherein said weighted averaging means is an R-2R network, said R-2R network comprises a plurality of resistors.