Soft strat bridge rectifier circuit

• US 6,009,008 A
• Filed: 03/31/1998
• Issued: 12/28/1999
• Est. Priority Date: 03/31/1997
• Status: Expired due to Fees

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Pelly, Brian R.
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/052,271
• Time in Patent Office: 637 Days
• Field of Search: 363/125, 363/126, 363/127, 363/128, 363/49, 363/81, 363/84, 363/53
• US Class Current: 363/125
• CPC Class Codes: H02H 7/125 for rectifiers
• CPC Class Codes: H02H 9/001 limiting speed of change of electric quantities, e.g. soft switching on or off progressive control of electronic switches for eliminating interferences H03K17/16
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 7/125 Avoiding or suppressing excessive transient voltages or currents

Abstract

A soft start bridge rectifier circuit is described for controlling the operation of the bridge rectifier in order to ramp up the DC output upon connection with the AC input in order to limit in-rush current. Additionally, short-circuit/overload protection, temporary line loss protection and undervoltage checking circuitry is provided.

Claims

1. A rectifier circuit for converting power from an AC source having one or more phases to DC power having a voltage (Vo) from a Vo+ node to a Vo- node, the rectifier circuit comprising:

at least first and second rectifier legs coupled from the Vo- node to the Vo+ node, each rectifier leg including a diode and a silicon controlled rectifier (SCR), respective anodes of the diodes being coupled to the Vo- node, respective cathodes of the diodes being coupled to respective anodes of the SCRs at respective AC input nodes, and respective cathodes of the SCRs being coupled to the Vo+ node; and

a gate drive circuit operable to permit one or more of the SCRs to fire at respective one or more firing angles during half cycles of respective phases of the AC source, the gate drive circuit including a ramp circuit having;

a first integrator circuit operable to produce ramp pulses corresponding to respective integrals of the half cycles of the one or more phases of the AC source;

a peak detector circuit operable to produce Vp;

a second integrator circuit operable to produce a ramp signal (Vramp corresponding to an integal of Vp;

a comparator circuit operable to produce pulsed output signals corresponding with comparisons of the respective ramp pulses with the difference of Vp and Vramp, the pulsed output signals corresponding with the respective firing angles of the SCRs,

the firing angles of the gate drive circuit limiting the one or more SCRs to fire (i) only at respective firing angles between about 90°

to 180°

when Vo is below a predetermined value; and

(ii) at firing angles progressively lower than 180°

as Vo ramps up from a voltage below the predetermined value to progressively higher values.

2. The rectifier circuit of claim 1, wherein the gate drive circuit permits the respective firing angles to be progressively lower than 180°

as Vo ramps up from a voltage below the predetermined value to progressively higher values.

3. The rectifier circuit of claim 2, wherein the gate drive circuit permits substantially unrestricted firing of the one or more SCRs when Vo has reached or exceeded the predetermined value.

4. The rectifier circuit of claim 3, wherein the gate drive circuit permits substantially unrestricted firing of the one or more SCRs when Vo has met or exceeded the predetermined value for a predetermined period of time.

5. The rectifier circuit of claim 4, wherein the predetermined period of time is about 10 ms.

6. The rectifier circuit of claim 3, wherein the one or more phases of the AC source have a respective peak voltage (Vp), the predetermined value being about 75% of Vp.

7. The rectifier circuit of claim 1, wherein the firing angles begin when the respective ramp pulses substantially meet or exceed the difference of Vp and Vramp.

8. The rectifier circuit of claim 1, further comprising an overcurrent protection circuit operable to reset Vramp when Vo is smaller than Vramp-(Vp-V∫

pk) by a predetermined amount, where V∫

pk corresponds with the integral of the ramp pulses.

9. The rectifier circuit of claim 8, wherein the predetermined amount is a fraction of Vp.

10. The rectifier circuit of claim 9, wherein the fraction of Vp is about 75%.

11. The rectifier circuit of claim 1, further comprising a loss of phase circuit operable to reset Vramp when one or more voltages across respective SCRs falls below a predetermined threshold.

12. The rectifier circuit of claim 11, wherein the one or more voltages are averaged, the loss of phase circuit resetting Vramp when the average voltage across the SCRs falls below the predetermined threshold.

13. A rectifier circuit for converting power from a three phase AC source to DC power having a voltage (Vo) from a Vo+ node to a Vo- node, the rectifier circuit comprising:

first, second, and third rectifier legs coupled from the Vo- node to the Vo+ node, each rectifier leg including a diode and a silicon controlled rectifier (SCR), respective anodes of the diodes being coupled to the Vo- node, respective cathodes of the diodes being coupled to respective anodes of the SCRs at respective AC input nodes, and respective cathodes of the SCRs being coupled to the Vo+ node;

a gate drive circuit operable to permit the SCRs to fire at respective firing angles during half cycles of the respective phases of the AC source, the gate drive circuit including a ramp circuit having;

first, second, and third integrator circuits operable to produce ramp pulses corresponding to integrals of the half cycles of the respective phases of the AC source;

a peak detector circuit operable to produce Vp;

a fourth integrator circuit operable to produce a ramp signal (Vramp corresponding to an integral of Vp;

a comparator circuit operable to produce three pulsed output signals, each pulsed output signal corresponding with a comparison of a respective ramp pulse with the difference of Vp and Vramp, the pulsed output signals corresponding with the respective firing angles of the SCRs,

the gate drive circuit limiting the SCRs to turn on (i) only at respective firing angles between about 90°

to 180°

when Vo is below a predetermined value; and

(ii) at firing angles progressively lower than 180°

as Vo ramps up from a voltage below the predetermined value to progressively higher values.

14. The rectifier circuit of claim 13, wherein the gate drive circuit permits the respective firing angles to be progressively lower than 180°

as Vo ramps up from a voltage below the predetermined value to progressively higher values.

15. The rectifier circuit of claim 14, wherein the gate drive circuit permits substantially unrestricted firing of the SCRs when Vo has reached or exceeded the predetermined value.

16. The rectifier circuit of claim 15, wherein the gate drive circuit permits substantially unrestricted firing of the SCRs when Vo has met or exceeded the predetermined value for a predetermined period of time.

17. The rectifier circuit of claim 16, wherein the predetermined period of time is about 10 ms.

18. The rectifier circuit of claim 15, wherein the three phases of the AC source have a respective peak voltage (Vp), the predetermined value being about 75% of Vp.

19. The rectifier circuit of claim 13, wherein the respective firing angles begin when the respective ramp pulses substantially meet or exceed the difference of Vp and Vramp.

20. The rectifier circuit of claim 13, further comprising an overcurrent protection circuit operable to reset Vramp when Vo is smaller than Vramp-(Vp-V∫

pk) by a predetermined amount, where V∫

pk corresponds with the integral of the ramp pulses.

21. The rectifier circuit of claim 20, wherein the predetermined amount is a fraction of Vp.

22. The rectifier circuit of claim 21, wherein the fraction of Vp is about 75%.

23. The rectifier circuit of claim 13, further comprising a loss of phase circuit operable to reset Vramp when at least one voltage across the SCRs falls below a predetermined threshold.

24. The rectifier circuit of claim 23, wherein the voltages across the SCRs are averaged, the loss of phase circuit resetting Vramp when the average voltage across the SCRs falls below the predetermined threshold.

25. A rectifier circuit for converting power from an AC source having one or more phases to DC power having a voltage (Vo) from a Vo+ node to a Vo- node, the rectifier circuit comprising:

at least first and second rectifier legs coupled from the Vo- node to the Vo+ node, each rectifier leg including a diode and a silicon controlled rectifier (SCR), respective anodes of the diodes being coupled to the Vo- node, respective cathodes of the diodes being coupled to respective anodes of the SCRs at respective AC input nodes, and respective cathodes of the SCRs being coupled to the Vo+ node;

a gate drive circuit operable to permit the SCRs to fire at respective firing angles during half cycles of the phases of the AC source, the gate drive circuit including a ramp circuit having;

a first integrator circuit operable to produce ramp pulses corresponding to an integral of the half cycles of the one phase of the AC source;

a peak detector circuit operable to produce Vp;

a second integrator circuit operable to produce a ramp signal (Vramp corresponding to an integral of Vp;

a comparator circuit operable to produce a pulsed output signal corresponding with a comparison of the ramp pulses with the difference of Vp and Vramp, the pulsed output signal corresponding with the firing angle of the one SCR,

the gate drive circuit permitting only one SCR to fire (i) at a firing angle between about 90°

to 180° and

prohibiting other SCRs from firing when Vo is below a predetermined value; and

(ii) at firing angles progressively lower than 180°

as Vo ramps up from a voltage below the predetermined value to progressively higher values.

26. The rectifier circuit of claim 25, wherein the gate drive circuit permits the firing angle to be progressively lower than 180°

as Vo ramps up from a voltage below the predetermined value to progressively higher values.

27. The rectifier circuit of claim 26, wherein the gate drive circuit permits substantially unrestricted firing of the one SCR when Vo has reached or exceeded the predetermined value.

28. The rectifier circuit of claim 27, wherein the gate drive circuit permits substantially unrestricted firing of the one SCR when Vo has met or exceeded the predetermined value for a predetermined period of time.

29. The rectifier circuit of claim 28, wherein the predetermined period of time is about 10 ms.

30. The rectifier circuit of claim 27, wherein the one or more phases of the AC source have a respective peak voltage (Vp), the predetermined value being about 75% of Vp.

31. The rectifier circuit of claim 25, wherein the firing angle begins when the ramp pulses substantially meet or exceed the difference of Vp and Vramp.

32. The rectifier circuit of claim 25, further comprising an overcurrent protection circuit operable to reset Vramp when Vo is smaller than Vramp-(Vp-V∫

pk) by a predetermined amount, where V∫

pk corresponds with the integral of the ramp pulses.

33. The rectifier circuit of claim 32, wherein the predetermined amount is a fraction of Vp.

34. The rectifier circuit of claim 33, wherein the fraction of Vp is about 75%.

35. The rectifier circuit of claim 25, further comprising a loss of phase circuit operable to reset Vramp when one or more voltages across respective SCRs falls below a predetermined threshold.

36. The rectifier circuit of claim 35, wherein the one or more voltages are averaged, the loss of phase circuit resetting Vramp when the average voltage across the SCRs falls below the predetermined threshold.

37. A rectifier circuit for converting power from a three phase AC source to DC power having a voltage (Vo) from a Vo+ node to a Vo- node, the rectifier circuit comprising:

first, second, and third rectifier legs coupled from the Vo- node to the Vo+ node, each rectifier leg including a diode and a silicon controlled rectifier (SCR), respective anodes of the diodes being coupled to the Vo- node, respective cathodes of the diodes being coupled to respective anodes of the SCRs at respective AC input nodes, and respective cathodes of the SCRs being coupled to the Vo+ node;

a gate drive circuit operable to permit the SCRs to fire at respective firing angles during half cycles of the respective phases of the AC source, the gate drive circuit limiting the SCRs to turn on (i) only at respective firing angles between about 90°

to 180°

when Vo is below a predetermined value; and

(ii) at firing angles progressively lower than 180°

as Vo ramps up from a voltage below the predetermined value to progressively higher values.