Erase verify scheme for NAND flash

• US 6,009,014 A
• Filed: 06/03/1998
• Issued: 12/28/1999
• Est. Priority Date: 06/03/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hollmer, Shane C., Hu, Chung-You, Le, Binh Q., Chen, Pau-Ling, Su, Jonathan, Gutala, Ravi, Bill, Colin
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/090,296
• Time in Patent Office: 573 Days
• Field of Search: 365/185.01, 365/185.22, 365/185.29, 365/218, 365/185.26, 365/185.33
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

Claims

1. A method of erase verifying for a NAND string, said string comprising a plurality of floating gate transistors coupled between a string-select transistor and a ground-select transistor, said method comprising:

applying a first voltage to the select gate of the string-select transistor;

applying a second voltage to the select gate of the ground-select transistor;

applying a sensing current to the drain of the string-select transistor;

applying a non-negative erase verify voltage to the control gate of the floating gate transistors;

applying a bias voltage to the source of the ground-select transistor; and

detecting whether the sensing current flows through the NAND string.

2. The method of claim 1, wherein said first and second voltages turn on said string-select and said ground-select transistors, respectively.

3. The method of claim 1, wherein said erase verify voltage is approximately 0 volts.

4. The method of claim 1, wherein said bias voltage is positive.

5. The method of claim 1, wherein said NAND string is properly erased when the sensing current is detected and not properly erased when the sensing current is not detected.

6. The method of claim 1, wherein the detecting detects whether the entire sensing current flows through the NAND string.

7. The method of claim 6, wherein said NAND string is properly erased when the entire sensing current is detected and not properly erased when the entire sensing current is not detected.

8. The method of claim 1, wherein said NAND string is properly erased when all the floating gate transistors have erased threshold voltages less than or equal to a desired erased threshold voltage.

9. The method of claim 8, wherein said desired erased threshold voltage is the erase verify voltage minus the bias voltage minus the amount of overdrive needed to sink the entire sensing current.

10. A method of minimizing overerase of a NAND string, said string comprising a plurality of floating gate transistors coupled between a string-select transistor and a ground-select transistor, said method comprising:

performing an erase operation on said NAND string;

performing an erase verify operation on said NAND string, said erase verify operation comprising;

applying a first voltage to the select gate of the string-select transistor;

applying a second voltage to the select gate of the ground-select transistor;

applying a sensing current to the drain of the string-select transistor;

applying a non-negative erase verify voltage to the control gate of the floating gate transistors;

applying a bias voltage to the source of the ground-select transistor; and

detecting whether the sensing current flows through the NAND string; and

if no current is detected, performing a series of erase operations followed by said erase verify operation until the sensing current is detected.

11. The method of claim 10, wherein said erase verify voltage is approximately 0 volts.

12. The method of claim 10, wherein said bias voltage is positive.

13. The method of claim 10, wherein said performing a series of erase operations followed by said erase verify operation is performed until the entire sensing current is detected.

14. The method of claim 10, wherein said NAND string is properly erased when all the floating gate transistors have erased threshold voltages less than or equal to a desired erased threshold voltage.

15. The method of claim 14, wherein said desired erased threshold voltage is the erase verify voltage minus the bias voltage minus the amount of overdrive needed to sink the entire sensing current.