Semiconductor memory device having dynamic data amplifier circuit capable of reducing power dissipation
First Claim
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1. A semiconductor memory device comprising:
- a pair of data input/output lines;
a data amplifier circuit, connected to said data input/output lines, for amplifying voltages at said data input/output lines;
a data maintaining circuit, connected to said data amplifier circuit, for maintaining output signals of said data amplifier circuit; and
a data determination circuit, connected between said data maintaining circuit and said data amplifier circuit, for generating a data determination signal after said data maintaining circuit maintains the output signals of said data amplifier circuit and transmitting said data determination signal to said data amplifier circuit, so that an operation of said data amplifier circuit is suspended.
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Abstract
In a semiconductor memory device including a pair of data input/output lines, a data amplifier circuit amplifies voltages at the data input/output lines, and a data maintaining circuit maintains output signals of the data amplifier circuit. A data determination circuit, generates a data determination signal after the data maintaining circuit manintains the output signals of the data amplifier circuit and transmits the data transmitting the data determination signal to the data amplifier circuit, thus suspending the operation of the data amplifier circuit.
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Citations
10 Claims
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1. A semiconductor memory device comprising:
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a pair of data input/output lines; a data amplifier circuit, connected to said data input/output lines, for amplifying voltages at said data input/output lines; a data maintaining circuit, connected to said data amplifier circuit, for maintaining output signals of said data amplifier circuit; and a data determination circuit, connected between said data maintaining circuit and said data amplifier circuit, for generating a data determination signal after said data maintaining circuit maintains the output signals of said data amplifier circuit and transmitting said data determination signal to said data amplifier circuit, so that an operation of said data amplifier circuit is suspended. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification