Semiconductor memory device having dynamic data amplifier circuit capable of reducing power dissipation

• US 6,009,020 A
• Filed: 03/12/1999
• Issued: 12/28/1999
• Est. Priority Date: 03/13/1998
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nagata, Kyoichi
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/266,731
• Time in Patent Office: 291 Days
• Field of Search: 365/189.05, 365/207, 365/208, 365/194
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

In a semiconductor memory device including a pair of data input/output lines, a data amplifier circuit amplifies voltages at the data input/output lines, and a data maintaining circuit maintains output signals of the data amplifier circuit. A data determination circuit, generates a data determination signal after the data maintaining circuit manintains the output signals of the data amplifier circuit and transmits the data transmitting the data determination signal to the data amplifier circuit, thus suspending the operation of the data amplifier circuit.

Claims

1. A semiconductor memory device comprising:

a pair of data input/output lines;

a data amplifier circuit, connected to said data input/output lines, for amplifying voltages at said data input/output lines;

a data maintaining circuit, connected to said data amplifier circuit, for maintaining output signals of said data amplifier circuit; and

a data determination circuit, connected between said data maintaining circuit and said data amplifier circuit, for generating a data determination signal after said data maintaining circuit maintains the output signals of said data amplifier circuit and transmitting said data determination signal to said data amplifier circuit, so that an operation of said data amplifier circuit is suspended.

2. The device as set forth in claim 1, wherein said data determination circuit generates said data determination signal when a definite time period has passed after said data maintaining circuit maintains the output signals of said data amplifier circuit.

3. The device as set forth in claim 1, wherein said data maintaining circuit and said data determination circuit are reset by receiving a precharging signal.

4. The device as set forth in claim 1, wherein said data amplifier circuit comprises:

a first current mirror type differential amplifier for amplifying a first difference between the output voltages of said data input/output lines; and

a second current mirror type differential amplifier for amplifying a second difference opposite to said first difference between the output voltages of said data input/output lines,

said first and second current mirror type differential amplifiers being operated by said data determination circuit.

5. The device as set forth in claim 3, wherein said data maintaining circuit comprises:

a first flip-flop connected to an output of said first current mirror type differential amplifier and having a set terminal for receiving an output signal of said first current mirror type differential amplifier and a reset terminal for receiving a precharging signal; and

a second flip-flop connected to an output of said second current mirror type differential amplifier and having a set terminal for receiving an output signal of said second current mirror type differential amplifier and a reset terminal for receiving said precharging signal.

6. The device as set forth in claim 5, wherein each of first and second flip-flops comprises:

a first NAND circuit having a first input connected to said set terminal and a second input;

a delay circuit connected to an output of said first NAND circuit; and

a second NAND circuit having a first input for receiving said precharging signal and a second input connected to said delay circuit.

7. The device as set forth in claim 6, wherein said data determination circuit is connected to outputs of said second NAND circuits of said first and second flip-flops.

8. The device as set forth in claim 6, wherein said data determination circuit comprises an AND circuit having first and second inputs connected to outputs of said second NAND circuits of said first and second flip-flops, respectively, and a third input for receiving said precharging signal.

9. The device as set forth in claim 1, further comprising:

an equalizer, connected to said data input/output lines, for equalizing the voltages at said data input/output lines; and

a control circuit, connected to said data determination circuit and said equalizer, for operating said equalizer in accordance with said data determination signal and said precharging signal.

10. The device as set forth in claim 1, further comprising:

memory cells;

column selection circuits, operatively connected to said data input/output lines, for transmitting data from said memory cells to said data input/output lines; and

column selection drivers, each connected to said data determination circuit and one of said column selection circuits, for driving said column selection circuits,

said column selection drivers being operated in accordance with said data determination signal.