Supply line controlled sense amplifier
First Claim
1. A DRAM comprising:
- an array having a plurality of columns of memory cells;
a plurality of sense circuits coupled to respective ones of said plurality of columns;
a first bias transistor connecting said sense circuits to a first voltage supply;
a second bias transistor connecting said sense circuits to a second voltage supply; and
means for controlling current flow through said bias transistors in response to a detection signal indicative of the voltage level of said first voltage supply such that said bias transistors provide more current to said sense circuits when said voltage supply falls below a predetermined threshold voltage and provides less current to said sense circuits when said voltage supply exceeds said predetermined threshold voltage.
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0 Petitions
Accused Products
Abstract
A sense amplifier includes cross-coupled latch has a PMOS bias transistor for selectively connecting the cross-coupled latch to a supply voltage and has an NMOS bias transistor for selectively connecting the cross-coupled latch to ground potential. The conductivity of the PMOS bias transistor is controlled by a first bias signal having a magnitude dependent upon the supply voltage and, in a similar manner, the conductivity of the NMOS bias transistor is controlled by a second bias signal also having a magnitude dependent upon the supply voltage. When the supply voltage exceeds a predetermined level, the first and second bias signals are of respective magnitudes so as to slowly turn on the PMOS and NMOS bias signals. In this manner, the current flow is gradually increased to the sense circuit at high voltages, thereby minimizing noise and power consumption. When, on the other hand, the supply voltage drops below the predetermined level, the first and second bias signals are of respective magnitudes so as to rapidly turn on the PMOS and NMOS bias transistor potential. In this manner, current flow to the sense circuit is maximized at low supply voltages, thereby improving speeds at low supply voltages.
7 Citations
15 Claims
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1. A DRAM comprising:
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an array having a plurality of columns of memory cells; a plurality of sense circuits coupled to respective ones of said plurality of columns; a first bias transistor connecting said sense circuits to a first voltage supply; a second bias transistor connecting said sense circuits to a second voltage supply; and means for controlling current flow through said bias transistors in response to a detection signal indicative of the voltage level of said first voltage supply such that said bias transistors provide more current to said sense circuits when said voltage supply falls below a predetermined threshold voltage and provides less current to said sense circuits when said voltage supply exceeds said predetermined threshold voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of sourcing current to sense circuits coupled to bit lines of a memory cell array, said method comprising the steps of:
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determining whether a supply voltage exceeds a predetermined threshold voltage; and adjusting a rate of current flow from said supply voltage to said sense amplifiers in response to said determining step.
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Specification