Memory device

• US 6,009,036 A
• Filed: 06/29/1998
• Issued: 12/28/1999
• Est. Priority Date: 10/30/1996
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Takasugi, Atsushi
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/101,003
• Time in Patent Office: 547 Days
• Field of Search: 365/230.01, 365/185.01, 365/189.02, 365/189.05, 365/205
• US Class Current: 365/230.01
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

The object of the present invention is to provide a memory with reduced port area and excellent cost performance by combining a conventional multiport DRAM with a DRAM used as a temporary buffer, without losing the strong points of a conventional multiport DRAM, and in order to achieve that object, a memory of the present invention has a multiport DRAM and a general purpose DRAM having consecutive X addresses, common Y address and common control terminals, in order to promote efficient refresh control.

Claims

1. A semiconductor memory device capable of random access, comprising:

address generator, provided with external address signals, for generating an internal X address and an internal Y address;

serial address generating means for generating a serial address;

a single port first memory composition section, comprised of a first memory array having memory unit groups, for connecting first X decoder means supplied with said internal X address and first Y decoder means supplied with said internal Y address, and a first data bus connected to said first Y decoder means;

a two port second memory composition section, comprised of a second memory array having memory unit groups for connecting second X decoder means supplied with said internal X address and second Y decoder means supplied with said internal Y address, a second data bus connected to said second Y decoder means and connected to said first data bus, data register means for connecting to said second memory array, serial decoder means for connecting to said data register means and supplied with said serial address, and a third data bus connected to said serial decoder means;

first input means having input output terminals for connecting a mutually connected first data bus and a second data bus;

second input output means having at least output terminals for connecting to a third data bus;

control signal generating means, supplied with external control signals for controlling a memory comprising the above structural elements, for generating internal control signals for controlling memory peripheral circuits capable of memory access.

2. The memory device as disclosed in claim 1, wherein an X address for selecting said first memory composition section and an X address for selecting said second memory composition section are consecutive.

3. The memory device as disclosed in claim 2, having externally input control signals for controlling said first memory composition section, and externally input control signals for controlling said second memory composition section, and these control signals are common.

4. The memory device as disclosed in claim 3, wherein a Y address input to said first Y decoder means and a Y address input to said second Y decoder means are common.

5. The memory device as disclosed in claim 1, further comprising refresh means connected to said first X decoder means and said second X decoder means.

6. The memory device as disclosed in claim 5, wherein an X address for selecting said first memory composition section and an X address for selecting said second memory composition section are consecutive.

7. The memory device as disclosed in claim 6, having externally input control signals for controlling said first memory composition section, and externally input control signals for controlling said second memory composition section, and these control signals are common.

8. The memory device as disclosed in claim 7, wherein a Y address input to said first Y decoder means and a Y address input to said second Y decoder means is common.