Method and circuit for trimming the internal timing conditions of a semiconductor memory device

• US 6,009,041 A
• Filed: 02/26/1998
• Issued: 12/28/1999
• Est. Priority Date: 02/26/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Rolandi, Paolo, Fontana, Marco, Montanaro, Massimo, Barcella, Antonio
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/032,272
• Time in Patent Office: 670 Days
• Field of Search: 365/233.5, 365/233, 365/230.08
• US Class Current: 365/233.5
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.

Claims

1. A method for controlling the internal timing conditions for a semiconductor memory device including a memory matrix, said method comprising the steps of:

detecting each transition of a plurality of address terminals of the semiconductor memory device;

generating an address transition detection (ATD) synchronization signal in response to the transition detecting;

generating an equalization (EOU) signal activated by said ATD signal;

generating an OUTLATCH signal activated by said ATD signal and said EQU signal to enable an output buffer circuitry of the semiconductor memory device; and

automatically trimming the timing of said ATD, EQU and OUTLATCH signals according to a corresponding code contained in said semiconductor memory device.

2. The method according to claim 1, wherein the timing of said ATD, EQU and OUTLATCH signals are each regulated by a distinct transistor array having a variable equivalent resistance controlled by the corresponding code.

3. A circuit for detecting the optimal timing conditions for a semiconductor memory device which comprises a memory matrix, a plurality of address input signals and circuit portions for allowing reading of the data stored in the memory matrix, the circuit comprising:

an address transition detection (ATD) generator detecting each transition of a plurality of address input signals of the semiconductor memory device to produce an ATD synchronization signal;

an equalization generator activated by said ATD synchronization signal for generating an equalization signal for equalizing a sense amplifier in the semiconductor memory device;

an enabling generator receiving said ATD signal and generating an enable signal for enabling an output buffer circuitry of the semiconductor memory device; and

wherein

said semiconductor memory device includes a latch configured to store timing data therein representing one or more pulse width values for programmably trimming the ATD, equalization and enable signals.

4. The circuit according to claim 3, wherein said latch includes an array of flip-flops, each of which receives an address input signal corresponding to a distinct circuit portion of the memory device.

5. A device for controlling control signals internal to a semiconductor memory device having input address terminals, a memory array and an output buffer, comprising:

detecting circuitry for detecting an edge transition appearing on at least one of the input address terminals; and

address pulse circuitry for generating an address transition detection (ATD) pulse signal responsive to the detecting circuitry, a pulse width of the ATD pulse signal being programmable.

6. The device of claim 5, further including:

conditioning pulse circuitry for generating a conditioning pulse signal for conditioning circuitry associated with a bit line in the memory array, a pulse width of the conditioning pulse signal being programmable.

7. The device of claim 6, wherein:

the conditioning pulse circuitry is responsive to the address pulse circuitry.

8. The device of claim 6, further including:

enable pulse circuitry for generating an enable pulse signal for enabling the output buffer of the semiconductor memory device, a pulse width of the enable pulse signal being programmable.

9. The device of claim 8, wherein:

the enable pulse circuitry is responsive to the conditioning pulse circuitry.

10. The device of claim 8, further including:

storage circuitry for storing a plurality of codes, each code corresponding to a distinct one of the address pulse circuitry, the conditioning pulse circuitry and the enable pulse circuitry for determining a pulse width generated thereby.

11. The device of claim 10, wherein:

the address pulse circuitry, the conditioning pulse circuitry and the enable pulse circuitry each includes a transistor array; and

transistors in each transistor array are activated based upon the code corresponding thereto.

12. A circuit for controlling the generation of control signals internal to a semiconductor memory device having a plurality of address input signals, comprising:

first circuitry for storing one or more codes in the semiconductor memory device;

second circuitry for detecting an edge transition appearing on one or more of the address input signals; and

third circuitry, responsive to the second circuitry, for generating an address transition detect (ATD) pulse signal, timing characteristics of the ATD pulse being based upon the one or more codes stored by the first circuitry.

13. The circuit of claim 12, wherein:

a timing delay between the detection of the address input signal edge transition and an edge of the ATD pulse signal is based upon a first code stored by the first circuitry.

14. The circuit of claim 13, wherein:

at least one first code signal corresponding to the first code drives a control electrode of at least one transistor within the third circuitry for effecting an edge transition delay of the ATD pulse signal.

15. The circuit of claim 12, further including:

fourth circuitry, responsive to the third circuitry, for generating a conditioning pulse signal for conditioning at least one bit line in the memory array, timing characteristics of the conditioning pulse signal being based upon the one or more stored codes.

16. The circuit of claim 15, wherein:

the third circuitry generates the ATD pulse signal having a leading edge and a trailing edge; and

the fourth circuitry generates the conditioning pulse signal having a leading edge and a trailing edge, wherein the timing delay between the trailing edge of the ATD pulse signal and the trailing edge of the conditioning pulse signal is based upon a first code stored by the first circuitry.

17. The circuit of claim 15, further including:

fifth circuitry, responsive to the fourth circuitry, for generating an enable pulse signal for enabling output buffer circuitry of the semiconductor memory device, timing characteristics of the enable pulse signal being based upon the one or more stored codes.

18. The circuit of claim 17, wherein:

the fourth circuitry generates the conditioning pulse signal having a leading edge and a trailing edge;

the fifth circuitry generates the enable pulse signal having a leading edge and a trailing edge, wherein the timing delay between the trailing edge of the conditioning pulse signal and the trailing edge of the enable pulse signal is based upon a first code stored by the first circuitry.

19. The circuit of claim 17, wherein:

the third circuitry, fourth circuitry and fifth circuitry each includes a transistor array; and

the first circuitry stores a plurality of codes in the semiconductor memory device, each code activating transistors of a distinct transistor array for effecting an edge transition time of the output thereof.

20. A method of controlling the generation of control signals internal to a semiconductor memory device, comprising the steps of:

storing one or more codes in the semiconductor memory device;

detecting an edge transition appearing on one or more address input signals; and

generating an address transition detect (ATD) pulse signal, timing characteristics of the ATD pulse being based upon the one or more codes stored in the step of storing.

21. The method of claim 20, wherein:

the generating step includes the step of delaying the generation of an edge of the ATD pulse signal by an amount that is based upon a code stored during the step of storing.

22. The method of claim 20, further including the step of:

generating a conditioning pulse signal for conditioning at least one bit line in the semiconductor memory device, based upon the one or more codes stored during the step of storing.

23. The method of claim 20, wherein:

the step of generating the conditioning pulse signal includes the step of delaying the generation of an edge of the conditioning pulse signal relative to the generation of a corresponding edge of the ATD pulse signal by an amount that is based upon the one or more codes stored during the step of storing.

24. The method of claim 22, further including the step of:

generating an enable pulse signal for enabling an output buffer in the semiconductor memory device, based upon the one or more codes stored during the step of storing.

25. The method of claim 24, wherein:

the step of generating the enable pulse signal includes the step of delaying the generation of an edge of the enable pulse signal relative to the generation of a corresponding edge of the conditioning pulse signal by an amount that is based upon the one or more codes stored during the step of storing.

26. The method of claim 24, wherein:

the step of storing comprises the step of individually storing a plurality of codes in the semiconductor memory device, each code indicating a timing delay utilized during the generation of a distinct one of the ATD pulse signal, the conditioning pulse signal and the enable pulse signal.

27. The method of claim 20, further comprising the steps of:

replacing the stored one or more codes in the semiconductor memory device with one or more replacement codes; and

repeating the step of generating the ATD pulse signal, timing characteristics of the ATD pulse signal being based upon the one or more replacement codes.