Zero-IF receiver

• US 6,009,126 A
• Filed: 08/01/1997
• Issued: 12/28/1999
• Est. Priority Date: 09/06/1996
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Van Bezooijen, Adrianus
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Maddox, Michael W.
• Application Number:
  US08/904,381
• Time in Patent Office: 879 Days
• Field of Search: 375/319, 375/316, 375/324, 375/345, 375/349, 375/325, 329/318, 329/319, 329/306, 329/307, 329/304, 455/310, 455/303, 455/304, 455/306
• US Class Current: 375/319
• CPC Class Codes: H03D 2200/0084 Lowering the supply voltage and saving power
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

Known is a zero intermediate frequency receiver or zero-IF receiver in which DC-offset correction is done in the I- and Q-paths, after mixing down of the received RF-signal or of an IF-signal. Such a DC-offset correction is not sufficient for high gain I- and Q-paths, particularly not in pagers for receiving long messages. Furthermore, no optimal power saving is achieved if such a receiver alternately operates in receive mode and sleep mode. A zero intermediate frequency receiver is proposed in which DC-offset correction is distributed over the high gain I- and Q-path. Preferably, blocking means are provided between DC-offset correction circuits and low pass filters in the I- and Q-path to prevent that an output signal of an upstream DC-offset correction circuit in the path excites a downstream low pass filter in the path during DC-offset correction. Herewith, considerable power savings are achieved.

Claims

1. A zero intermediate frequency receiver comprising a local frequency generating arrangement which is coupled to a pair of quadrature related mixers for mixing down a received signal to a pair of quadrature related signals to be demodulated in an in-phase signal path and in a quadrature signal path, a path comprising a cascade of at least one low pass filter and at least two amplifiers, and a first DC-offset correction circuit between the amplifiers, characterized in that the path comprises at least a second DC-offset correction circuit which is distributed over the path for allowing the path to have a high gain.

2. A zero intermediate frequency receiver according to claim 1, wherein the receiver is arranged to activate the DC-offset correction circuits sequentially.

3. A zero intermediate frequency receiver according to claim 1, wherein the second DC-offset correction circuit is coupled in the cascade before a first low pass filter of the at least one low pass filter.

4. A zero intermediate frequency receiver according to claim 3, wherein a second low pass filter of the at least one low pass filter is coupled to an output of the first DC-offset correction circuit, whereby the first low pass filter has a lower selectivity than the second low pass filter.

5. A zero intermediate frequency receiver according to claim 3, wherein the path comprises blocking means to prevent that an output signal of a upstream DC-offset correction circuit in the path excites an downstream low pass filter in the path during DC-offset correction.

6. A zero intermediate frequency receiver according to claim 5, wherein the blocking means comprises at least a first clamp circuit which is coupled to an input of the first low pass filter.

7. A zero intermediate frequency receiver according to claim 6, wherein the path comprises a first buffer amplifier for isolating the second DC-offset correction circuit from the first clamp circuit.

8. A zero intermediate frequency receiver according to claim 5, wherein the blocking means comprises a second clamp circuit which is coupled to an input of the second low pass filter.

9. A zero intermediate frequency receiver according to claim 8, wherein the path comprises a second buffer amplifier for isolating the first DC-offset correction circuit from the second clamp circuit.

10. A zero intermediate frequency receiver according to claim 1, wherein the receiver is arranged for operating in a power saving mode, whereby at least bias currents of at least the amplifiers, filters and DC-offset correction circuits are switched off if the receiver is in the power saving mode.

11. A zero intermediate frequency receiver according to claim 1, wherein the DC-offset correction circuits are droop-less sample-and-hold circuits.

12. A zero intermediate frequency receiver according to claim 11 wherein the droop-less sample-and-hold circuits are formed by a subtracter comprised in the path and a cascade of an analog-to-digital converter, a latch circuit, and a digital-to-analog converter coupled in a loop with the subtracter, an output of the digital-to-analog converter being coupled to a subtraction input of the subtracter.

13. A zero intermediate frequency receiver according to claim 12, wherein a low pass filter is provided between the output of the digital-to-analog converter and the subtraction input of the subtracter.

14. A zero intermediate frequency receiver according to claim 12, wherein the cascade is an analog-to-digital converter of the successive approximation type.