Synchronizer
First Claim
1. A synchronizer comprising:
- a transmission pattern detection circuit for detecting a known transmission pattern transmitted from a transmitter and generating a transmission pattern detection information signal upon detection of said known transmission pattern;
a difference detection circuit for detecting a difference between a reference timing of said transmitter and a reference timing of a receiver on the basis of a receiving time of said known transmission pattern;
an average value calculation circuit for calculating an average value of said difference detected in said difference detection circuit and updating said calculated average value only upon receipt of said transmission pattern detection information signal from said transmission pattern detection circuit;
an integration circuit for determining an integrated value by integrating said average value for each time of interrupting said receiver; and
a correction value calculation circuit for calculating a correction value used to correct the reference timing of said receiver in a forward direction in the case where said integrated value exceeds a predetermined first threshold level, and to correct the reference timing of said receiver backward in the case where said integrated value is reduced below a predetermined second threshold level.
1 Assignment
0 Petitions
Accused Products
Abstract
A detection circuit of a synchronizer detects a difference between a reference timing of a transmitter and a reference timing of a receiver based on a time of receiving a known transmission pattern sent from the transmitter. An average value calculation circuit calculates an average value of the difference detected by the detection circuit. An integration circuit determines an integrated value by integrating the average value each time of interrupting the receiver. A correction value calculation circuit calculates a correction value to correct the reference timing of the receiver in forward direction in the case where the integrated value exceeds a predetermined first threshold level and to correct the reference timing of the receiver backward in the case where the integrated value is reduced below a predetermined second threshold level.
-
Citations
78 Claims
-
1. A synchronizer comprising:
-
a transmission pattern detection circuit for detecting a known transmission pattern transmitted from a transmitter and generating a transmission pattern detection information signal upon detection of said known transmission pattern; a difference detection circuit for detecting a difference between a reference timing of said transmitter and a reference timing of a receiver on the basis of a receiving time of said known transmission pattern; an average value calculation circuit for calculating an average value of said difference detected in said difference detection circuit and updating said calculated average value only upon receipt of said transmission pattern detection information signal from said transmission pattern detection circuit; an integration circuit for determining an integrated value by integrating said average value for each time of interrupting said receiver; and a correction value calculation circuit for calculating a correction value used to correct the reference timing of said receiver in a forward direction in the case where said integrated value exceeds a predetermined first threshold level, and to correct the reference timing of said receiver backward in the case where said integrated value is reduced below a predetermined second threshold level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78)
-
-
13. A synchronizer provided in a receiver, comprising:
-
a transmission pattern detection circuit for detecting a known transmission pattern transmitted from a transmitter and generating a transmission pattern detection information signal upon detection of said transmission pattern; a timing difference detection circuit for detecting a difference between a reference timing of said transmitter and a reference timing of said receiver on the basis of a receiving time of said transmission pattern; an average value calculation circuit for calculating an average value of said detected difference and updating said calculated average value only upon receipt of said transmission pattern detection information signal from said transmission pattern detection circuit; an integration circuit for determining an integrated value by integrating said average value for each time of interrupting said receiver; and a correction value calculation circuit for calculating a correction value to correct the reference timing of said receiver in forward direction in the case where said integrated value exceeds a predetermined first threshold level and to correct the reference timing of said receiver backward in the case where said integrated value is reduced below a predetermined second threshold level. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
-
-
24. A synchronizer provided in a receiver, comprising:
-
a transmission pattern detection circuit for detecting a known transmission pattern transmitted from a transmitter and generating a transmission pattern detection information signal upon detection of said transmission pattern; a first timing difference detection circuit for detecting a first difference between the reference timing of said transmitter and the reference timing of said receiver on the basis of the receiving time of said transmission pattern using a high-accuracy reference clock; a first average value calculation circuit for calculating a first average value of said detected first difference; a first integration circuit for determining a first integrated value by integrating said first average value for each time of interrupting said receiver; a first correction value calculation circuit for calculating a first correction value to correct the reference timing of said receiver in forward direction in the case where said first integrated value exceeds a predetermined first threshold level and to correct the reference timing of said receiver backward in the case where said first integrated value is reduced below a predetermined second threshold level; a second timing difference detection circuit for detecting a second difference between the reference timing of said transmitter and the reference timing of said receiver based on the receiving time of said transmission pattern using a low-accuracy reference clock; a second average value calculation circuit for calculating a second average value of said detected second difference; a second integration circuit for determining a second integrated value by integrating said second average value for each time of interrupting said receiver; and a second correction value calculation circuit for calculating a second correction value to correct the reference timing of said receiver in forward direction in the case where said second integrated value exceeds a predetermined third threshold level and to correct the reference timing of said receiver backward in the case where said second integrated value is reduced below a predetermined fourth threshold level; wherein the reference timing of said receiver is corrected based on said first correction value and said second correction value is calculated by said second correction value calculation circuit in a continuous receiving mode, and the reference timing of said receiver is corrected based on said second correction value in an intermittent receiving mode.
-
Specification