Methods, apparatus and computer program products for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices

• US 6,009,252 A
• Filed: 03/05/1998
• Issued: 12/28/1999
• Est. Priority Date: 03/05/1998
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Avant! Corporation (Synopsys Incorporated)
• Inventors: Lipton, Gary Bruce
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PRUESSNER, MARCEL W
• Application Number:
  US09/035,271
• Time in Patent Office: 663 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/500.05, 395/500.06, 395/500.07
• US Class Current: 716/112
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to generate color symmetrizing matrices corresponding to respective child cells in the integrated circuit schematic. Here, the child cells are characterized as having a number of symmetrical configurations which at a port level are electrically equivalent. Operations are also performed to generate a first color symmetry vector for a child cell in the integrated circuit schematic and a second color symmetry vector for the corresponding child cell in the integrated circuit layout. A vector equivalency is also preferably determined by comparing a product of the color symmetrizing matrix and the first color symmetry vector against a product of the color symmetrizing matrix and the second color symmetry vector. Notwithstanding the presence of a vector equivalency, a possibility may still exist that with respect to the corresponding symmetric child cells in the schematic and layout, isomorphism between the schematic and layout is not present. To address this possibility, an operation is preferably performed to detect the absence of a spurious symmetry in the color symmetrizing matrix. If an absence is detected, the presence of the vector equivalency will unequivocally establish the one-to-one correspondence with respect to the child cells being analyzed. Thus, the need to perform a computationally expensive membership test to determine whether a selected permutation can be derived from valid symmetries, can be successfully eliminated. The preferred comparison tool also infers symmetries, where available, so that symmetries of a child cell may be propagated to a parent cell when the tool is evaluating a grandparent cell containing the parent cell.

Claims

1. A method of determining equivalency between an integrated circuit schematic and an integrated circuit layout, comprising the steps of:

representing the integrated circuit schematic as a hierarchical schematic netlist having a child cell and a parent cell containing the child cell;

extracting the integrated circuit layout as a hierarchical layout netlist having a child cell and a parent cell containing the child cell;

generating a color symmetrizing matrix corresponding to one of the child cells in the hierarchical schematic netlist and the hierarchical layout netlist;

generating a schematic graph of the parent cell in the hierarchical schematic netlist;

generating a layout graph of the parent cell in the hierarchical layout netlist;

coloring the vertices in the schematic graph and generating a first color symmetry vector for the child cell therein;

coloring the vertices in the layout graph and generating a second color symmetry vector for the child cell therein;

determining an equivalency between the colors of the vertices in the schematic graph and the colors of the vertices in the layout graph;

determining a vector equivalency between a product of the color symmetrizing matrix and the first color symmetry vector and a product of the color symmetrizing matrix and the second color symmetry vector; and

detecting absence of a spurious symmetry in the color symmetrizing matrix if a vector equivalency is determined.

2. The method of claim 1, wherein said step of determining a vector equivalency comprises determining a vector equivalency if and only if an equivalency between the colors of the vertices in the circuit schematic graph and the colors of the vertices in the layout graph exists.

3. The method of claim 1, wherein said step of generating a color symmetrizing matrix comprises generating a color symmetrizing matrix corresponding to the child cell in the hierarchical schematic netlist.

4. The method of claim 3, wherein said representing step comprises representing the integrated circuit schematic as a hierarchical schematic netlist having a plurality of child cells and a parent cell containing the plurality of child cells;

and wherein said extracting step comprises extracting the integrated circuit layout as a hierarchical layout netlist having a plurality of child cells and a parent cell containing the plurality of child cells.

5. The method of claim 4, wherein said step of coloring the vertices in the schematic graph comprises coloring the vertices in the schematic graph and generating a respective first color symmetry vector for each of the child cells in the schematic graph of the parent cell in the hierarchical schematic netlist;

and wherein said step of coloring the vertices in the layout graph comprises coloring the vertices in the layout graph and generating a respective second color symmetry vector for each of the child cells in the layout graph of the parent cell in the hierarchical layout netlist.

6. The method of claim 1, wherein said step of detecting absence of a spurious symmetry comprises the steps of:

determining a number of actual symmetries of the color symmetrizing matrix; and

determining whether the number of actual symmetries of the color symmetrizing matrix is equivalent to a number of desired symmetries.

7. The method of claim 6, wherein said step of detecting absence of a spurious symmetry comprises performing a membership test if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

8. The method of claim 7, wherein said step of performing a membership test comprises performing a Schreier-Simms operation if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

9. The method of claim 1,

wherein said step of determining a vector equivalency comprises determining a vector equivalency if and only if an equivalency between the colors of the vertices in the circuit schematic graph and the colors of the vertices in the layout graph exists;

wherein said step of generating a color symmetrizing matrix comprises generating a color symmetrizing matrix corresponding to the child cell in the hierarchical schematic netlist; and

wherein said step of detecting absence of a spurious symmetry comprises the steps of determining a number of actual symmetries of the color symmetrizing matrix; and

determining whether the number of actual symmetries of the color symmetrizing matrix is equivalent to a number of desired symmetries.

10. The method of claim 9, wherein said step of detecting absence of a spurious symmetry comprises performing a membership test if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

11. The method of claim 10, wherein said step of performing a membership test comprises performing a Schreier-Simms operation if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

12. A method of determining equivalency between an integrated circuit schematic and an integrated circuit layout, comprising the steps of:

generating a color symmetrizing matrix corresponding to a child cell in the integrated circuit schematic;

generating a first color symmetry vector for the child cell in the integrated circuit schematic;

generating a second color symmetry vector for a child cell in the integrated circuit layout;

determining a vector equivalency between a product of the color symmetrizing matrix and the first color symmetry vector and a product of the color symmetrizing matrix and the second color symmetry vector; and

detecting absence of a spurious symmetry in the color symmetrizing matrix if a vector equivalency is determined.

13. The method of claim 12, wherein said step of detecting absence of a spurious symmetry comprises the steps of:

determining a number of actual symmetries of the color symmetrizing matrix; and

determining whether the number of actual symmetries of the color symmetrizing matrix is equivalent to a number of desired symmetries.

14. The method of claim 13, wherein said step of detecting absence of a spurious symmetry comprises performing a membership test if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

15. The method of claim 14, wherein said step of performing a membership test comprises performing a Schreier-Simms operation if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

16. A method of determining equivalency between an integrated circuit schematic and an integrated circuit layout, comprising the steps of:

representing the integrated circuit schematic as a hierarchical schematic netlist having a child cell, a parent cell containing the child cell and a grandparent cell containing the parent cell;

extracting the integrated circuit layout as a hierarchical layout netlist having a child cell, a parent cell containing the child cell and a grandparent cell containing the parent cell;

propagating a symmetry of the child cell to the parent cell in the hierarchical schematic netlist;

generating a color symmetrizing matrix corresponding to the parent cell in the hierarchical schematic netlist;

generating a schematic graph of the grandparent cell in the hierarchical schematic netlist;

generating a layout graph of the grandparent cell in the hierarchical layout netlist;

coloring the vertices in the schematic graph and generating a first color symmetry vector for the parent cell therein;

coloring the vertices in the layout graph and generating a second color symmetry vector for the parent cell therein;

determining an equivalency between the colors of the vertices in the schematic graph and the colors of the vertices in the layout graph; and

determining a vector equivalency between a product of the color symmetrizing matrix and the first color symmetry vector and a product of the color symmetrizing matrix and the second color symmetry vector.

17. The method of claim 16, further comprising the step of detecting absence of a spurious symmetry in the color symmetrizing matrix if a vector equivalency is determined.

18. The method of claim 17, wherein said step of detecting absence of a spurious symmetry comprises the steps of:

determining a number of actual symmetries of the color symmetrizing matrix; and

determining whether the number of actual symmetries of the color symmetrizing matrix is equivalent to a number of desired symmetries.

19. The method of claim 18, wherein said step of detecting absence of a spurious symmetry comprises performing a membership test if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

20. The method of claim 19, wherein said step of performing a membership test comprises performing a Schreier-Simms operation if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

21. A computer program product for determining equivalency between an integrated circuit schematic and an integrated circuit layout, comprising a computer readable storage medium having computer-readable program code means embodied in said medium, said computer-readable program code means comprising:

computer-readable program code means for representing the integrated circuit schematic as a hierarchical schematic netlist having a child cell and a parent cell containing the child cell;

computer-readable program code means for extracting the integrated circuit layout as a hierarchical layout netlist having a child cell and a parent cell containing the child cell;

computer-readable program code means for generating a color symmetrizing matrix corresponding to one of the child cells in the hierarchical schematic netlist and the hierarchical layout netlist;

computer-readable program code means for generating a schematic graph of the parent cell in the hierarchical schematic netlist;

computer-readable program code means for generating a layout graph of the parent cell in the hierarchical layout netlist;

computer-readable program code means for coloring the vertices in the schematic graph and generating a first color symmetry vector for the child cell therein;

computer-readable program code means for coloring the vertices in the layout graph and generating a second color symmetry vector for the child cell therein;

computer-readable program code means for determining an equivalency between the colors of the vertices in the schematic graph and the colors of the vertices in the layout graph;

computer-readable program code means for determining a vector equivalency between a product of the color symmetrizing matrix and the first color symmetry vector and a product of the color symmetrizing matrix and the second color symmetry vector; and

computer-readable program code means detecting absence of a spurious symmetry in the color symmetrizing matrix if a vector equivalency is determined.

22. The computer program product of claim 21, wherein said computer-program product code means for determining a vector equivalency comprises computer-program product code means for determining a vector equivalency if and only if an equivalency between the colors of the vertices in the circuit schematic graph and the colors of the vertices in the layout graph exists.

23. The computer program product of claim 21, wherein said computer-program product code means for detecting absence of a spurious symmetry comprises computer-program product code means for determining a number of actual symmetries of the color symmetrizing matrix and determining whether the number of actual symmetries of the color symmetrizing matrix is equivalent to a number of desired symmetries.

24. The computer program product of claim 23, wherein said computer-program product code means for detecting absence of a spurious symmetry comprises computer-program product code means for performing a membership test if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

25. The computer program product of claim 24, wherein said computer-program product code means for performing a membership test comprises computer-program product code means for performing a Schreier-Simms operation if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

26. An apparatus for determining equivalency between an integrated circuit schematic and an integrated circuit layout, comprising:

means for generating a color symmetrizing matrix corresponding to a child cell in the integrated circuit schematic;

means for generating a first color symmetry vector for the child cell in the integrated circuit schematic;

means for generating a second color symmetry vector for a child cell in the integrated circuit layout;

means for determining a vector equivalency between a product of the color symmetrizing matrix and the first color symmetry vector and a product of the color symmetrizing matrix and the second color symmetry vector; and

means for detecting absence of a spurious symmetry in the color symmetrizing matrix if a vector equivalency is determined.

27. The apparatus of claim 26, wherein said means for detecting absence of a spurious symmetry comprises means for determining a number of actual symmetries of the color symmetrizing matrix and determining whether the number of actual symmetries of the color symmetrizing matrix is equivalent to a number of desired symmetries.

28. The apparatus of claim 27, wherein said means for detecting absence of a spurious symmetry comprises means for performing a membership test if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

29. The apparatus of claim 28, wherein said means for performing a membership test comprises means for performing a Schreier-Simms operation if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

30. A computer program product for determining equivalency between an integrated circuit schematic and an integrated circuit layout, comprising a computer-readable storage medium having computer-readable program code embodied in said medium, said computer-readable program code comprising:

computer-readable program code that generates a color symmetrizing matrix corresponding to a child cell in the integrated circuit schematic;

computer-readable program code that determines a vector equivalency between a product of the color symmetrizing matrix and a first color symmetry vector for the child cell in the integrated circuit schematic and a product of the color symmetrizing matrix and a second color symmetry vector for a child cell in the integrated circuit layout; and

computer-readable program code that detects absence of a spurious symmetry in the color symmetrizing matrix if a vector equivalency is determined.

31. The computer program product of claim 30, wherein said computer-readable program code that detects absence of a spurious symmetry comprises:

computer-readable program code that determines a number of actual symmetries of the color symmetrizing matrix; and

computer-readable program code that determines whether the number of actual symmetries of the color symmetrizing matrix is equivalent to a number of desired symmetries.

32. The computer program product of claim 31, wherein said computer-readable program code that detects absence of a spurious symmetry comprises:

computer-readable program code that performs a membership test if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.

33. The computer program product of claim 32, wherein said computer-readable program code that performs a membership test comprises computer-readable program code that performs a Schreier-Simms operation if the number of actual symmetries of the color symmetrizing matrix is greater than the number of desired symmetries.