Spare repeater amplifiers for long lines on complex integrated circuits

• US 6,009,253 A
• Filed: 06/20/1996
• Issued: 12/28/1999
• Est. Priority Date: 06/20/1996
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Srivatsa, Chakra R., Bauman, James A.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/669,897
• Time in Patent Office: 1,286 Days
• Field of Search: 364/488-491, 375/214, 455/16, 370/226, 370/227, 330/124 D, 385/46, 395/500.07, 395/500.09, 395/500.13, 395/500.06
• US Class Current: 327/285
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

An IC includes a plurality of functional blocks each having a discrete block-level architecture. The functional blocks are connected to one another via metal interconnect lines defined by an interconnect architecture. One or more of the functional blocks includes a spare (i.e., unused) repeater amplifier. Where a repeater amplifier inserted in a particular long line of the interconnect structure would decrease the signal propagation delay through the long line, the interconnect architecture is modified so that the long line is routed through the spare repeater amplifier. Such modification decreases the signal propagation delay of the long line without requiring a modification of the block-level architecture.

Claims

1. An integrated circuit comprising:

a first functional block-level architecture surrounded by a first border, and including at least one output node, the first border encompassing a block-level circuit architecture defining a function of the first functional block-level architecture;

a second functional block-level architecture surrounded by a second border, the second border encompassing a block-level circuit architecture defining a function of the second functional block-level architecture and including a plurality of individual repeater amplifiers with each individual repeater amplifier having an input terminal and an output terminal;

wherein the input terminal and the output terminal of each individual repeater amplifier in said plurality of repeater amplifiers each extend to the second border;

a third functional block-level architecture having at least one input node;

a first line connected between the at least one output node of the first functional block-level architecture and the at least one input terminal of one repeater amplifier in said plurality of repeater amplifiers; and

a second line connected between the output terminal of the one repeater amplifier and the at least one input node of the third functional block-level architecture.

2. The circuit of claim 1, wherein the first and second lines are metal conductors.

3. The circuit of claim 1 further comprising a common voltage node, wherein said input terminal of each said individual repeater amplifier in said plurality of individual repeater amplifiers is connected to a common voltage.

4. The circuit of claim 3 wherein the common voltage node is a ground plane.

5. A method of optimizing a signal propagation delay period of a signal path on an integrated circuit, the signal path being defined between an output node of a first functional block-level architecture on the integrated circuit and an input node of a second functional block-level architecture on the integrated circuit, the integrated circuit further including a third functional block-level architecture, the method comprising:

designing a circuit architecture for the third functional block-level architecture, the circuit architecture including a plurality of individual spare repeater amplifiers with each spare repeater amplifier having an input terminal and an output terminal;

wherein the input terminal and the output terminal of each spare repeater amplifier in said plurality of individual spare repeater amplifiers extend to a border of said third functional block-level architecture;

calculating a delay period associated with a first conductor connected between the output node of the first functional block-level architecture and the input node of the second functional block-level architecture;

forming a second conductor connected between the output node of the first functional block-level architecture and the input terminal of one spare repeater amplifier of the third functional block-level architecture and forming a third conductor between the output terminal of the spare repeater amplifier and the input node of the second functional block-level architecture upon determining that use of the one spare repeater amplifier with said second and third conductors results in another delay period between said output node and said input node that is less than said delay period, wherein the first conductor is defined by an interconnect architecture, and further wherein the interconnect architecture is modified to define the second and third connector without modifying the circuit architecture for the third functional block-level architecture.

6. The method of claim 5, wherein the second and third conductors are formed using a metallization process.

7. The method of claim 5, wherein the delay period is calculated using circuit analysis tools on a simulated version of the integrated circuit.