Simulation/emulation system and method

• US 6,009,256 A
• Filed: 05/02/1997
• Issued: 12/28/1999
• Est. Priority Date: 05/02/1997
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Axis Systems Incorporated (Cadence Systems, Inc.)
• Inventors: Wang, Steven, Tsay, Ren-Song, Sun, Richard Yachyang, Tseng, Ping-Sheng, Lin, Sharon Sheau-Pyng, Shen, Quincy Kun-Hsu, Tsai, Mike Mon Yen
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Knox, Lonnie A.
• Application Number:
  US08/850,136
• Time in Patent Office: 970 Days
• Field of Search: 340/825, 364/490, 364/488, 364/489, 364/578, 364/579, 364/221.2, 364/232.3, 371/23, 371/22.1, 371/22.2, 371/16.2, 395/500, 395/183
• US Class Current: 703/13
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. Each mode or combination of modes provides the following main features or combinations of main features: (1) switching among modes, manually or automatically; (2) compilation process to generate software models and hardware models; (3) component type analysis for generating hardware models; (4) software clock set-up to avoid race conditions through, in one embodiment, gated clock logic analysis and gated data logic analysis; (5) software clock implementation through, in one embodiment, clock edge detection in the software model to trigger an enable signal in the hardware model, send signal from the primary clock to the clock input of the clock edge register in the hardware model via the gated clock logic, send a clock enable signal to the enable input of the hardware model'"'"'s register, send data from the primary clock register to the hardware model'"'"'s register via the gated data logic, and reset the clock edge register disabling the clock enable signal to the enable input of the hardware model'"'"'s registers; (6) log selective data for debug sessions and post-simulation analysis; and (7) combinational logic regeneration.

Claims

1. A method of simulating a circuit in a simulation system, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising steps:

determining component type in the hardware language;

generating a software model of the circuit;

generating a hardware model of at least a portion of the circuit based on component type automatically; and

simulating the behavior of the circuit with the software model and the hardware model by providing input data.

2. The method of claim 1, further comprising steps:

controlling the software model and the hardware model with a software kernel.

3. The method of claim 2, wherein the step of controlling further comprises steps:

determining the presence of input data to the simulation system;

evaluating clock components;

propagating input data to the hardware model;

detecting active clock edge of the clock components in the software model; and

evaluating the input data with the hardware model in response to the active clock edge detection.

4. The method of claim 1, wherein the step of simulating further comprises:

simulating the behavior of the circuit with the software model for a time period; and

simulating the behavior of the circuit with the hardware model for another time period to accelerate the simulation process.

5. A method of simulating a circuit, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising steps:

generating a software model of the circuit;

generating a hardware model of the circuit;

simulating a behavior of the circuit with the software model by providing input data to the software model;

selectively switching to the hardware model through software control;

providing input data to the hardware model; and

evaluating the input data in the hardware model based on the detection of a trigger event in the software model.

6. The method of claim 5, wherein the step of generating the hardware model further comprises steps:

determining component type in the hardware language; and

generating the hardware model based on component type.

7. The method of claim 5, further comprising steps:

selectively switching to the software model; and

simulating a behavior of the circuit with the software model by providing input data to the software model.

8. The method of claim 5, wherein the step of evaluating further comprises:

determining the presence of input data to the simulation system;

evaluating clock components;

propagating input data to the hardware model;

detecting the trigger event, wherein the trigger event includes an active clock edge of the clock components; and

evaluating the input data with the hardware model in response to the active clock edge detection.

9. A method of simulating a circuit, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising steps:

generating a software model of the circuit;

generating a hardware model of at least a portion of the circuit;

providing test bench data to the hardware model from a first test point to a second test point;

simulating a behavior of the circuit with the hardware model from the first test point to the second test point;

loading hardware state values at the second test point from the hardware model to the software model;

providing test bench data to the software model from the second test point to a third test point; and

simulating a behavior of the circuit with the software model from the second test point to the third test point.

10. The method of claim 9, wherein the step of generating a hardware model further comprises:

determining component type in the hardware language; and

configuring the hardware model automatically based on the component type.

11. The method of claim 9, wherein the step of simulating with the hardware model further comprising steps:

detecting clock data in the software model; and

simulating the behavior of the circuit in the hardware model in response to the detection in the software model.

12. A method of simulating a circuit in the environment of the circuit'"'"'s target system, comprising steps:

generating a software model of the circuit;

generating a hardware model of at least a portion of the circuit;

providing input signals from the target system to the hardware model;

providing output signals from the hardware model to the target system;

detecting an evaluation trigger event in the software model;

simulating a behavior of the circuit with the hardware model in response to the detection of the evaluation trigger event in the software model, where the software model is capable of controlling the simulation.

13. The method of claim 12, wherein the evaluation trigger event includes an active clock edge and the step of simulating further comprises:

generating a clock data from the software model;

detecting an active clock edge of the clock data in the software model; and

evaluating the input signals from the target system to the hardware model with the hardware model in response to the active clock edge detection.

14. A method of evaluating data in a circuit during a simulation process, comprising:

generating a software model of the circuit;

generating a hardware model of at least a portion of the circuit;

propagating data to the hardware model until the data stabilizes;

detecting a clock edge in the software model;

evaluating data with the hardware model in response to the clock edge detection in the software model and in synchronization with a hardware-generated clock signal.

15. A method of controlling a simulation system, the simulation system having a software model and a hardware model of a circuit to be simulated, comprising steps:

evaluate clock components;

detect a clock edge in the software model;

update registers and combinational components in the hardware model in response to the clock edge detection in the software model; and

advance simulation time.

16. A simulation system operating in a host computer system for simulating a behavior of a circuit, the host computer system including a central processing unit (CPU), main memory, and a local bus coupling the CPU to main memory and allowing communication between the CPU and main memory, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:

a software model of the circuit coupled to the local bus;

software control logic coupled to the software model and a hardware logic element, for controlling the operation of the software model and said hardware logic element; and

said hardware logic element coupled to the local bus and including a hardware model of at least a portion of the circuit configured automatically based on component type.

17. The system of claim 16, wherein the software control logic further comprises:

interface logic which is capable of receiving input data and a clock data from an external process, and

clock detection logic for detecting an active edge of the clock data and generating a trigger signal.

18. The system of claim 17, wherein the hardware logic element further comprises:

clock enable logic for evaluating data in the hardware model in response to the trigger signal.

19. The system of claim 16, wherein the hardware logic element comprises a field programmable device.

20. The system of claim 16, wherein the hardware logic element comprises:

a plurality of field programmable devices coupled together, each field programmable device including a portion of the hardware model of the circuit;

a plurality of interconnections to couple the portions of the hardware model together, each interconnection representing a direct connection between field programmable devices, wherein the shortest path between any two field programmable devices is at most two interconnections.

21. A verification system operating in a host computer system for verifying a behavior of a circuit, the host computer system including a central processing unit (CPU), memory, and a local bus coupling the CPU to memory and allowing communication between the CPU and memory, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:

a software model of the circuit coupled to the local bus for evaluating input data;

a hardware logic element coupled to the local bus and including a hardware model of at least a portion of the circuit for evaluating the input data, said hardware model configured automatically in the hardware logic element; and

software control logic coupled to the software model and the hardware logic element, for controlling the operation of the software model and the hardware model in the hardware logic element, said software control logic further including,

switching logic for allowing a user to selectively switch between the software model and the hardware model for verifying the circuit, and

loading logic for loading hardware state values from the hardware model to the software model.

22. The verification system of claim 21, wherein the hardware logic element utilizes at least one data logic device for modeling at least a portion of the circuit for the hardware model, the data logic device includes a data input for receiving data to be evaluated, a data output for generating data that was evaluated by the data logic device, a clock input for receiving clock signals, and an enable input for enabling the operation of the data logic device.

23. The verification system of claim 22, wherein the software control logic further comprises software clock logic for controlling the advancement of simulation time in the hardware model, the software clock logic including:

software detection logic for detecting clock data in the software model and generating a corresponding trigger data, and

hardware detection logic for receiving the trigger data and generating an enable data to the enable input of the data logic device so that the data logic device can evaluate the input data in response to clock signals provided to the clock input of the data logic device.

24. A verification system operating in a host computer system for verifying a behavior of a circuit, the host computer system including a central processing unit (CPU), memory, and a system bus coupling the CPU to memory and allowing communication between the CPU and memory, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:

a software model of the circuit coupled to the system bus for receiving and evaluating a first set of user data in software;

a first bus coupled to the system bus;

a hardware accelerator coupled to the first bus and including;

a reconfigurable hardware element for modeling at least a portion of the circuit as a hardware model, receiving a second set of control data and a second set of user data, and evaluating the second set of user data, and

control logic for controlling the delivery of the second set of control data and the second set of user data between the software model and the hardware model;

software control logic coupled to the software model and the hardware accelerator, for controlling the operation of the software model and the hardware model in the hardware accelerator; and

configuration logic coupled to the software model and the hardware accelerator for configuring the reconfigurable hardware element with the hardware model automatically based on the circuit.

25. The verification system of claim 24, wherein the first bus is a Peripheral Component Interconnect (PCI) bus.

26. The verification system of claim 24, wherein the hardware accelerator further comprises a second bus for coupling the reconfigurable hardware element and the control logic so that the second set of control data and the second set of user data can be accessed between the CPU and the reconfigurable hardware element.

27. The verification system of claim 26, wherein the software model delivers the second set of user data to the hardware model via the control logic and the second bus.

28. The verification system of claim 26, wherein the reconfigurable hardware element is a field programmable gate array (FPGA) device.

29. The verification system of claim 26, wherein the configuration logic models combinational logic components with look-up tables in the reconfigurable hardware element.

30. The verification system of claim 26, wherein the hardware accelerator includes an interconnect bus system and the reconfigurable hardware element includes a plurality of field programmable gate array (FPGA) devices, wherein each FPGA device includes at least a portion of the hardware-modeled circuit, and the plurality of FPGA devices are coupled together through the interconnect bus system.

31. The verification system of claim 30, wherein each FPGA device includes communications logic circuits, and wherein the configuration logic further comprises:

stitching logic for configuring communications logic circuits in each FPGA device so that the second set of user data can be accessed between the CPU and the FPGA device via the second bus during a first period, and the plurality of FPGA devices can communicate among themselves via the interconnect bus during a second period.

32. The verification system of claim 31, wherein the first period and the second period are contiguous in time.

33. The verification system of claim 26, wherein the second bus includes a high bank bus coupled to at least one FPGA device and a low bank bus coupled to at least one FPGA device.

34. The verification system of claim 26, wherein the software control logic further comprises:

switching logic for allowing the user to selectively switch between the software model and the hardware model for verifying the circuit; and

loading logic for loading hardware state values from the hardware model to the software model.

35. The verification system of claim 34, wherein the reconfigurable hardware element uses registers for modeling portions of the circuit, and the software control logic further comprises:

regeneration logic for deriving combinational logic components from register values and providing combinational logic component values for access by the software control logic.

36. The verification system of claim 26, wherein the configuration logic further comprises:

stitching logic for configuring communications logic circuits in each FPGA device so that the second set of user data can be accessed between the CPU and the FPGA device via the second bus.

37. The verification system of claim 24, wherein the first set of user data is equal to the second set of user data.

38. The verification system of claim 24, wherein the first set of user data is different from the second set of user data.

39. The verification system of claim 24, wherein the first set of user data is presented contiguously in time with the second set of user data.

40. The verification system of claim 24, wherein the configuration logic further comprises:

stitching logic for configuring communications logic circuits in each reconfigurable hardware element so that the second set of user data can be accessed between the CPU and the reconfigurable hardware element.

41. A design verification system operating in a host computer system for verifying a behavior of a circuit design, the host computer system including a central processing unit (CPU), memory, and a system bus coupling the CPU to memory and allowing communication between the CPU and memory, the circuit design represented by a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:

a software simulator coupled to the system bus for generating a software model of the circuit design and for receiving and evaluating a first set of test data;

a hardware accelerator coupled to the system bus and including;

a first reconfigurable device for modeling at least a portion of the circuit design as a portion of a hardware model, and receiving and evaluating a second set of test data,

a second reconfigurable device for modeling another portion of the circuit design as another portion of the hardware model, and receiving and evaluating third set of test data,

a device controller coupled to the system bus for controlling the delivery of the second set of test data and third set of test data between the software simulator and the hardware accelerator, and

a device bus for coupling the first and second reconfigurable devices to the device controller;

software control logic coupled to the software simulator and the hardware accelerator, for controlling the operation of the software model and the hardware model; and

configuration logic coupled to the software simulator and the hardware accelerator for configuring the first and second reconfigurable devices with the hardware model based on the circuit design, and including stitching logic for configuring a first set of pointer circuits in the first reconfigurable device and a second set of pointer circuits in the second reconfigurable device for controlling the transfer of the second set of test data and the third set of test data between the software simulator and the hardware accelerator.

42. The design verification system of claim 41, further comprising:

an interconnect bus system for coupling the first reconfigurable device and the second reconfigurable device.

43. The design verification system of claim 42, wherein the device controller further comprises:

memory transfer logic for transferring the second set of test data between the software simulator and the first set of pointer circuits in the first reconfigurable device during a first time period via the device bus, and for transferring the third set of test data between the software simulator and the second set of pointer circuits in the second reconfigurable device during a second time period via the device bus.

44. The design verification system of claim 43, wherein the device controller further comprises:

evaluation logic for evaluating the second set of test data and the third set of test data in the first and second reconfigurable devices during a third time period and wherein data delivery between the first reconfigurable device and the second reconfigurable device occurs across the interconnect bus system.

45. The design verification system of claim 44, wherein the first time period, the second time period, and the third time period are sequential with respect to each other.