Trace synchronization in a processor

• US 6,009,270 A
• Filed: 12/17/1997
• Issued: 12/28/1999
• Est. Priority Date: 04/08/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mann, Daniel
• Primary Examiner(s): Downs, Robert W.
• Assistant Examiner(s): DAS, CHAMELI
• Application Number:
  US08/992,315
• Time in Patent Office: 741 Days
• Field of Search: 395/500, 395/183.21, 395/183.14, 395/704, 395/701, 395/702, 395/703, 395/709
• US Class Current: 717/128
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches

Abstract

A processor provides trace synchronization information to ensure that address information for reconstructing instruction execution flow is provided in trace records with sufficient frequency. A trace record is provided for instructions that change the program flow such as conditional branches. However, target address information is not provided in the trace record for such instructions as conditional branches, only an indication of whether the branch was taken. Target address information is provided, however, for those instructions in which the target address is in some way data dependent. The processor determines whether each trace record includes address information. Each trace entry providing address information causes a counter to be reloaded to a predetermined value which is the desired maximum number of trace records generated before current program address information is provided. The counter counts each trace record produced which does not include address information. When the count of such trace records reaches the predetermined number, trace logic provides the current program address as a trace entry, thereby providing trace synchronization information.

Claims

1. A method of operating a processor during a trace operation providing trace records indicative of instruction execution flow, the method comprising:

determining when a predetermined number of said trace records have been provided without address information; and

providing synchronizing address information in a trace record when said predetermined number of trace records have been provided without said address information, said synchronizing address information being indicative of a current program address being traced.

2. The method as recited in claim 1 wherein the operation of determining includes:

counting in a counter each time one of said trace records without address information is provided, until said predetermined number has been reached; and

wherein the counting starts over each time said processor provides address information as part of said trace record, thereby limiting a maximum number of said trace records provided without address information to said predetermined number of trace records.

3. The method as recited in claim 2 further comprising loading said predetermined number into a register in said processor.

4. The method as recited in claim 3 wherein said predetermined number is loaded into a register using a processor instruction.

5. The method as recited in claim 2 wherein said address information causing the counting to start over is a branch target address.

6. The method as recited in claim 1 wherein said synchronizing address information indicates a most recently executed instruction.

7. The method as recited in claim 1 further comprising storing said trace records including said synchronizing address information in a trace memory on said processor.

8. The method as recited in claim 7 wherein said trace information and said stored synchronizing address information in said trace memory is readable by said processor.

9. The method as recited in claim 1 further comprising providing said trace information to an external port of said processor.

10. The method as recited in claim 9 wherein said port is parallel.

11. The method as recited in claim 9 wherein said port is serial.

12. The method as recited in claim 1 wherein said trace record having synchronizing address information includes a first portion having a code indicating that said trace record includes synchronizing address information and a second portion providing said synchronizing address information.

13. A method of providing trace synchronization information on a processor, comprising:

setting a synchronization register to a first value, said first value indicating a maximum number of trace records to provide sequentially without address information, said address information indicative of a current location of program execution;

determining whether each of said trace records includes said address information;

reloading a counter to count to said first value each time it is determined that one of said trace records includes said address information;

counting in said counter each time one of said trace records does not include said address information; and

providing current program address information in a synchronizing trace record, when said counter indicates said first value has been counted, thereby providing said trace synchronization information.

14. The method as recited in claim 13 wherein said synchronization register is programmable.

15. The method as recited in claim 13 wherein said trace synchronization information is stored in a trace memory on said processor, said trace memory including a plurality of trace records indicating branch information, a plurality of trace records indicating target addresses for branches and said synchronizing trace record.

16. The method as recited in claim 15 wherein said synchronizing trace record includes a first portion having a code indicating that said synchronizing trace record includes synchronizing address information and a second portion providing said synchronizing address information.

17. The method as recited in claim 13 wherein said trace synchronization information is provided to a trace port, thereby providing said trace synchronization information external to the microprocessor.

18. A processor comprising:

a synchronizing register containing a first value;

a counter circuit coupled to said synchronizing register, said counter circuit receiving a count control signal causing said counter circuit to count and receiving a load signal causing said counter circuit to load an initial value, said counter circuit providing an output signal indicating when said first value has been counted;

trace logic coupled to said counter and receiving said output signal, said trace logic asserting said load signal when a trace record includes synchronizing address information and wherein said trace logic asserts said count control signal each time a trace record does not include said synchronizing address information and wherein said trace logic outputs a current program address indication in response to assertion of said output signal by said counter circuit.

19. The processor as recited in claim 18 wherein said synchronizing address information is provided as a trace record including a first portion having a code indicating that said current address information is synchronizing address information and a second portion providing said current program address indication.

20. The processor as recited in claim 18 further comprising a trace memory storing a plurality of trace information entries, including said synchronizing address information.

21. The processor as recited in claim 18 wherein said processor further comprises a trace port, programmably receiving said trace information entries.

22. A method comprising:

generating a stream of first trace records tracing program execution in a processor; and

inserting a synchronizing address trace record in the stream of first trace records, each of the first trace records lacking a program address, the synchronizing address trace record including program address information.

23. The method as recited in claim 22 wherein the synchronizing address trace record is inserted in the stream of first trace records in response to a counter counting a predetermined number of trace records lacking the program address.