Vehicle computer system with high speed data buffer and serial interconnect

• US 6,009,363 A
• Filed: 06/24/1996
• Issued: 12/28/1999
• Est. Priority Date: 11/29/1995
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Wong, William, Randall, Ron, Moeller, Mark M., Beckert, Richard D.
• Primary Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/668,781
• Time in Patent Office: 1,282 Days
• Field of Search: 701/29-33, 701/24, 701/35, 364/551.01, 340/439, 340/426, 340/691, 340/825.5, 340/310.1, 340/538, 340/825.25, 340/815.69, 361/686, 361/683, 361/680, 361/814, 361/679, 395/281, 395/290, 370/522, 370/476, 370/537, 455/345, 455/346, 455/349, 455/348, 307/10.7, 307/10.1
• US Class Current: 701/33
• CPC Class Codes: B60R 11/02 for radio sets, television sets, telephones, or the like; Arrangement of controls thereof
• CPC Class Codes: B60R 11/0211 for record carriers apparatus, e.g. video recorders, tape players or CD players
• CPC Class Codes: B60R 11/0229 for displays, e.g. cathodic tubes
• CPC Class Codes: B60R 11/0252 for personal computers, e.g. laptops, notebooks
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: B60R 2011/0005 Dashboard
• CPC Class Codes: B60R 2011/027 for Din-sized apparatus
• CPC Class Codes: B60R 25/00 Fittings or systems for preventing or indicating unauthorised use or theft of vehicles locks for vehicles E05B77/00-E05B85/00
• CPC Class Codes: B60T 2270/406 Test-mode; Self-diagnosis
• CPC Class Codes: G01C 21/3661 Guidance output on an external device, e.g. car radio
• CPC Class Codes: G01C 21/3688 Systems comprising multiple parts or multiple output devices (not client-server), e.g. detachable faceplates, key fobs or multiple output screens
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 67/01 Protocols
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04M 1/6041 Portable telephones adapted for handsfree use

Abstract

A vehicle computer system has a housing sized to be mounted in a vehicle dashboard or other appropriate location. The housing includes a base unit and a faceplate. A first logic unit is mounted to the base unit to form a support module. The support module has two interfacing slots and can support connections to multiple peripheral devices. The support module facilitates high speed data exchange between the peripheral devices for streaming continuous audio or video data. The support module has a fast data memory to temporarily hold data being communicated between the peripheral devices. The support module also has a memory access circuit associated with each of the peripheral devices which designates at least one storage area within the fast data memory to hold data received from, or to be sent to, the associated peripheral device. The vehicle computer has a computer module which can be connected to or removed from one interfacing slot of the support module. A multi-bit bus (e.g., PCI bus) interfaces the computer module and the support module. The vehicle computer system also has a logic unit mounted to the faceplate to form a faceplate module. This module is detachably connected to the other interfacing slot of the support module. When the faceplate module is attached, a high speed serial interface electronically couples the support module to the faceplate module. The high speed serial interface enables the logic units on the support and faceplate modules to exchange a high speed, synchronized, serial bit stream. This data stream is organized into multiple frames, with each frame having multiple data bits and at least one valid bit to indicate whether the data bits are valid.

Claims

1. A vehicle computer system comprising:

a housing of a size suitable to be mounted in a vehicle dashboard, the housing having first and second support structures that can be physically connected to, or separated from, one another;

a first logic unit mounted to the first support structure of the housing;

a second logic unit mounted to the second support structure of the housing;

a high speed serial interface to electrically interconnect the first and second logic units when the first and second support structures are physically connected to one another; and

the first and second logic units being configured to exchange data via the high speed serial interface using a synchronized serial bit stream which is organized into multiple frames, individual frames having multiple data bits and at least one valid bit to indicate whether the data bits are valid.

2. A vehicle computer system as recited in claim 1, wherein one of the first and second logic units transmits at least one synchronizing bit to commence a start of a frame and synchronize the serial bit stream.

3. A vehicle computer system as recited in claim 1, wherein each frame is a 17-bit frame consisting of 16 data bits and one valid bit.

4. A vehicle computer system as recited in claim 1, wherein the housing has a form factor of a single DIN.

5. A vehicle computer system as recited in claim 1, wherein the first support structure is configured to be mounted within the vehicle dashboard and the second support structure is a detachable faceplate.

6. A vehicle computer system as recited in claim 1, further comprising a power system comprising:

a backup power source; and

a power source selector coupled between (1) both the backup power source and a primary vehicle battery and (2) the vehicle computer system, the power source selector alternately enabling at least one of the primary vehicle battery or the backup power source to supply power to the vehicle computer system.

7. A vehicle computer system as recited in claim 1, wherein the first logic unit is configured to interface with multiple peripheral devices, and the first logic unit uses direct access memory to facilitate data communication with the peripheral devices.

8. In a vehicle computer system having a clock generator that generates clock pulses, a method for transmitting data comprising the step of serially sending one synchronizing bit every N clock pulses followed by an N-bit frame comprising N-1 data bits and one valid bit to indicate whether the data bits are valid, wherein N is an integer greater than one.

9. A method as recited in claim 8 wherein the multi-bit frame is a 17-bit frame consisting of 16 data bits and one valid bit.

10. A serial data stream transmitted over a serial conductor as a result of the step recited in claim 8.

11. A vehicle computer system programmed to perform the step recited in claim 8.

12. A vehicle computer power system for a vehicle computer system to be mounted in a vehicle, the vehicle having a primary power source, the power system comprising:

a secondary power source mounted external to the vehicle computer system;

a power source selector coupled between (1) both the primary and secondary power sources and (2) the vehicle computer system, the power source selector alternately enabling at least one of the primary power source or the secondary power source to supply power to the vehicle computer system;

the power source selector having a first diode path connected between the primary power source and the vehicle computer system, the first diode path having n diodes; and

the power source selector having a second diode path connected between the secondary power source and the vehicle computer system, the second diode path having at least n+1 diodes.

13. A vehicle computer system comprising a vehicle computer power system as recited in claim 12.

14. A vehicle computer system, comprising:

a housing of a size suitable to be mounted in a vehicle dashboard;

a logic unit mounted in the housing, the logic unit having an internal multi-bit bus structure and being configured to interface with one or more peripheral devices;

a processing unit mountable in the housing, the processing unit having an internal multi-bit bus structure separate from the bus structure of the logic unit;

a data memory operatively coupled to the bus structure of the logic unit to temporarily hold data being communicated between the peripheral devices, the data memory being partitioned into storage areas for corresponding ones of the peripheral devices; and

the logic unit having one or more memory access circuits associated with corresponding ones of the peripheral devices, each memory access circuit designating storage areas of the data memory to hold input data received from, or output data to be sent to, the associated peripheral device.

15. A vehicle computer system as recited in claim 14 wherein the logic unit and the processing unit are interfaced using a multi-bit bus.

16. A vehicle computer system for use in a vehicle, comprising:

a logic unit;

a data memory accessible by the logic unit to temporarily hold data being communicated between peripheral devices, the data memory being partitioned into storage areas for corresponding ones of the peripheral devices; and

the logic unit having one or more memory access circuits associated with corresponding ones of the peripheral devices, each memory access circuit designating one storage area of the data memory to hold input data received from the associated peripheral device and another storage area of the data memory to hold output data to be sent to the associated peripheral device.

17. A vehicle computer system as recited in claim 16 wherein the logic unit has an address/data bus structure and the data memory is coupled to the address/data bus structure, the memory access circuits being capable of accessing the data memory directly using the address/data bus structure.

18. A vehicle computer system as recited in claim 16 configured to support first and second peripheral devices, further comprising:

first and second memory access circuits associated with the first and second peripheral devices, respectively; and

the first memory access circuit being configured to designate a particular storage area of the data memory to hold data received from the first peripheral device and the second memory access circuit being configured to designate the same particular storage area of the data memory to hold data to be sent to the second peripheral device.

19. A vehicle computer system as recited in claim 16, further comprising a power system comprising:

a backup power source; and

a power source selector coupled between (1) both the backup power source and a primary vehicle battery and (2) the vehicle computer system, the power source selector alternately enabling at least one of the primary vehicle battery or the backup power source to supply power to the vehicle computer system.

20. In a vehicle computer system to be mounted in a vehicle, the vehicle computer system having a processing unit connected to communicate with multiple peripheral devices, a subsystem for processing continuous audio or video data received from a data source comprising:

a data processor;

a memory partitioned into pages;

a first memory access circuit associated with the data source to facilitate data transfer between the memory and the data source, the first memory access circuit being configured to input data received from the data source in a particular memory page; and

a second memory access circuit associated with the data processor to facilitate data transfer between the memory and the data processor, the second memory access circuit being configured to retrieve the data from the particular memory page and to output the data to the data processor.

21. A subsystem as recited in claim 20, wherein the data processor comprises a digital signal processor.

22. A vehicle computer system comprising a subsystem as recited in claim 20.

23. In a vehicle computer system to be mounted in a vehicle, the vehicle computer system supporting at least one peripheral device having a fixed clock frequency, a master clock generating unit comprising:

an oscillator to provide a fundamental clock frequency; and

clock frequency adjustment circuitry coupled to the oscillator to produce one or more master clock frequencies based upon the fundamental clock frequency, the clock frequency adjustment circuitry being adjustable to synchronize to the fixed clock frequency of the peripheral component.

24. A vehicle computer system comprising a subsystem as recited in claim 23.

25. A vehicle computer system comprising:

a housing having a base unit and a faceplate;

a logic unit mounted to the base unit to form a support module, the support module having an interfacing slot and being configured to support multiple peripheral devices;

the faceplate having at least one electronic component to form a faceplate module, the faceplate module being compatibly connected to the interfacing slot of the support module;

a high speed serial interface electronically coupling the logic unit to the electronic component on the faceplate module, the high speed serial interface enabling the logic unit to transfer a synchronized serial bit stream to the electronic component, the serial bit stream being organized into multiple frames, individual frames having multiple data bits and at least one valid bit to indicate whether the data bits are valid; and

the support module being configured to facilitate data communication between the peripheral devices, the support module having a data memory to temporarily hold data being communicated between the peripheral devices and one or more memory access circuits associated with corresponding ones of the peripheral devices, each memory access circuit designating at least one storage area within the data memory to hold input data received from, or output data to be sent to, the associated peripheral device.

26. A vehicle computer system as recited in claim 25, wherein the support module has another interfacing slot, and the vehicle computer system further comprises a computer module having a second processing unit, the computer module being compatibly connected to the other interfacing slot of the support module.

27. A vehicle computer system as recited in claim 26, wherein each of the first and second processing units has its own internal multi-bit bus.

28. A vehicle computer system as recited in claim 26, wherein each individual frame is a 17-bit frame consisting of 16 data bits and one valid bit.

29. A vehicle computer system as recited in claim 26, wherein the support module is configured to support first and second peripheral devices, further comprising:

first and second memory access circuits associated with the first and second peripheral devices, respectively; and

the first memory access circuit being configured to designate a particular storage area of the data memory to hold data received from the first peripheral device and the second memory access circuit being configured to designate the same particular storage area of the data memory to hold data to be sent to the second peripheral device.

30. A vehicle computer system as recited in claim 25, wherein the vehicle computer system is connected to receive power from a primary vehicle battery, and further comprising a power system comprising:

a backup power source; and

a power source selector coupled between (1) both the backup power source and the primary vehicle battery and (2) the vehicle computer system, the power source selector alternately enabling at least one of the primary vehicle battery or the backup power source to supply power to the vehicle computer system.

31. A vehicle computer system, comprising:

first and second logic units mountable in a vehicle;

a clock generator that generates clock pulses;

a high speed serial interface to electrically interconnect the first and second logic units; and

the first and second logic units being configured to exchange data via the high speed serial interface by sending one synchronizing bit every N clock pulses followed by an N-bit frame comprising N-1 data bits and one valid bit to indicate whether the data bits are valid, wherein N is an integer greater than one.