File array communications interface for communicating between a host computer and an adapter

• US 6,009,478 A
• Filed: 11/04/1997
• Issued: 12/28/1999
• Est. Priority Date: 11/04/1997
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Panner, Bryan K., Hoskins, Timothy Lee, Napolitano, Richard
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US08/963,902
• Time in Patent Office: 784 Days
• Field of Search: 707/1-10, 707/100-104, 707/200-206, 709/200-204, 709/217-219, 709/301-305, 710/5-7, 710/20-24, 710/33-35, 710/72-74, 710/129-130, 711/111-114
• US Class Current: 710/5
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: Y10S 707/99931 Database or file accessing

Abstract

A file array communications transport system transports unique packets between a host computer and an adapter of a data processing platform in accordance with a file array protocol. The protocol is manifested as an exchange of these unique packets and the file array transport comprises an arrangement of logic circuits and data structures needed to exchange these packets over a tightly-coupled, low latency interface of a file array storage architecture.

Claims

1. Apparatus for communicating between a host computer and an adapter of a data processing platform over an interface, the apparatus comprising:

communication regions in host memory of the host computer that are shared by the adapter and host computer, the communication regions comprising at least one placeholder for communicating an input/output (I/O) operation; and

a file array information block (FIB) referenced by the placeholder, the FIB containing information needed to execute the I/O operation between the host computer and the adapter.

2. The apparatus of claim 1 wherein the communication regions comprise host memory locations organized as independent command and response queues.

3. The apparatus of claim 2 further comprising a doorbell register for generating a unique interrupt to notify one of the host computer and adapter that there is a change in state of the placeholder in a queue.

4. The apparatus of claim 3 wherein the placeholder is a queue entry.

5. The apparatus of claim 3 wherein the queue entry comprises a size field and a pointer field.

6. The apparatus of claim 5 wherein contents of the size field specify a size of the referenced FIB and wherein contents of the pointer field specify an address of the referenced FIB in host memory.

7. The apparatus of claim 1 wherein the FIB comprises a header and a command-specific body.

8. The apparatus of claim 7 wherein the header comprises a xfstate field that identifies a communication nature of the FIB.

9. The apparatus of claim 8 wherein the header further comprises a command field containing routing information for the FIB.

10. The apparatus of claim 9 wherein the header further comprises a sender size field that specifies a maximum size of a command allocated by the host and transferred with the FIB.

11. The apparatus of claim 10 wherein the header further comprises a size field that specifies an actual size of the command transferred with the FIB.

12. The apparatus of claim 11 wherein the header further comprises a receiver address field that contains a logical address of the FIB in host memory.

13. The apparatus of claim 12 wherein the header further comprises a sender data field that is an additional placeholder for a sender to store data.

14. The apparatus of claim 7 wherein the command-specific body comprises a command field that indicates a request specified by the FIB.

15. The apparatus of claim 14 wherein the command-specific body further comprises a protocol field that contains protocol-specific information associated with the request.