Protected address range in an electrically erasable programmable read only memory

• US 6,009,495 A
• Filed: 11/08/1995
• Issued: 12/28/1999
• Est. Priority Date: 12/29/1989
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Packard Bell NEC
• Inventors: Gauthier, Lloyd W., Kohtz, Robert A., DeRoo, David T., Nicol, Mark D., DeLisle, David J., Fakhruddin, Saifuddin
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/554,667
• Time in Patent Office: 1,511 Days
• Field of Search: 395/800, 395/700, 395/500-545, 395/490, 395/726, 395/800.37, 365/195, 365/218, 365/185.04, 365/185.12, 365/189.01, 365/189.07, 365/230.03, 711/103, 711/163, 711/172, 711/130, 711/138, 711/152, 711/164, 711/170, 740/200, 712/37, 712/43, 712/220, 709/213, 713/1, 713/2, 713/100, 713/202, 380/4, 368/195
• US Class Current: 711/103
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

Claims

1. An apparatus for protecting writes to a programmable address range of a memory device, said programmable address range comprising an addressable area smaller than the total addressable area of said memory device, said memory device being readable and writable, said apparatus comprising:

means for defining a protected address range of said memory device, said protected address range being of a predetermined selectable variable size and adapted to be physically configurable in hardware;

means responsive to said defining means for decoding the address range defined by said defining means to generate an address decode signal in response to an address signal that corresponds to the protected address range;

means responsive to said address decode signal for preventing writes to the protected address range in said memory device while enabling data in the protected address range in said memory device to be read; and

means for programmably disabling said preventing means, said disabling means including means for allowing reads and writes to said protected address range in said memory device.

2. An apparatus in accordance with claim 1 wherein said defining means is determined from a digital code stored in a hardware register connected to said decoding means.

3. An apparatus in accordance with claim 2 wherein the bits of said hardware register are hand-wired to predetermined values.

4. An apparatus in accordance with claim 1 wherein said defining means defines a boot block for non-volatile boot-strap software for a computer system.

5. An apparatus in accordance with claim 4 wherein said boot block comprises a range of addresses according to said defining means.

6. An apparatus in accordance with claim 5 wherein said boot block comprises a hardware definable size according to said defining means.

7. An apparatus in accordance with claim 6 wherein said decoding means comprises a comparator for comparing addresses defmed by said defining means.

8. An apparatus in accordance with claim 7, wherein said comparator compares upper address bits to define addresses in an upper address space.

9. An apparatus in accordance with claim 7 wherein said defining means comprises a hardware register connected to said comparator.

10. A system for protecting a predetermined readable and programmable address range comprising:

at least one processor;

a memory device readable by said at least one processor;

said memory device being programmable by said at least one processor and responsive to a write enable strobe generated by said processor;

means for defining a protected address range within said memory device, said protected address range being of a predetermined selectable variable size and adapted to be physically configurable in hardware;

means for preventing software reconfiguration of said protected address range;

means responsive to address signals generated by said at least one processor which correspond to said protected address range in said memory device for protected address range in said memory device while enabling data in the protected address range to be read; and

means for disabling said preventing means, said disabling means allowing writes and reads to said protected address range in said memory device.

11. A system in accordance with claim 10, wherein said defining means includes a register having at least one data input adapted to be connected to a predetermined fixed logic signal.

12. A system in accordance with claim 11, including a central processing unit and a system control processor providing interfacing to peripherals in an IBM-compatible personal computer.

13. A system in accordance with claim 11, wherein said memory device is an electrically erasable, programmable, read-only memory.

14. A system in accordance with claim 12 wherein said inhibiting means further includes a comparator for comparing addresses generated by said computer with information stored in said register defining protected address signals.

15. A system in accordance with claim 14, wherein said inhibiting means further includes an AND gate for gating the output of said comparator with the write enable strobe to gate the write enable strobe to the electrically erasable programmable read-only memory.

16. A system for protecting a predetermined readable and programmable address range comprising:

at least one processor;

a memory device readable by said at least one processor;

said memory device being programmable by said at least one processor and responsive to a write enable strobe generated by said processor;

means for defining a protected address range within said memory device, said protected address range being of a programmably selectable variable size and adapted to be configured by hardware;

means responsive to address signals generated by said at least one processor which correspond to said protected address range in said memory device for preventing write commands to said memory at said protected address range in said memory device while enabling data in the protected address range to be read; and

means for disabling said preventing means, said disabling means allowing writes and reads to said protected address range in said memory device;

a main memory having more than one megabyte of addressable storage locations being selectable by at least 21 address lines A0-A20, wherein said computer includes a central processing unit (CPU) for processing data adapted to be coupled to at least one peripheral device by way of a predetermined keyboard interface, said CPU having at least two modes of operation, including a real mode of operation for accessing said main memory up to one megabyte and a protective mode of operation for accessing said main memory above one megabyte, said two modes of operation enabling said protected address to be configured at any address in said main memory, one of said two modes of operation adapted to be selected by one or more predetermined control signals, said CPU adapted to be reset by way of a predetermined reset signal, said main memory, said main memory and said CPU connected to a common bus, said system further comprising;

means for enabling said A20 address line for memory accesses over one megabyte in response to a hardware based Gate A20 control signal;

a system control processor (SCP) for communicating with said CPU and adapted to generate the reset signal for resetting said CPU under predetermined conditions; and

interfacing means interconnected between said CPU and said SCP for interfacing said CPU and said SCP for controlling communication between said CPU and said SCP and for emulating said predetermined keyboard interface, said interfacing means including predetermined hardware for enabling switching the mode of operation of said CPU from said real mode of operation to said protected mode of operation and for generating the hardware based Gate A20 signal for enabling said CPU to access main memory above one megabyte by automatically enabling said A20 address line in response to said hardware based Gate A20 control signal to enable relatively faster access to said protected address range while maintaining IBM PC-AT compatibility, said interfacing means further including means for enabling either said SCP or said CPU to generate said reset signal.

17. A method of protecting a predetermined readable and programmable address range in a readable and programmable memory device, comprising the steps of:

defining a programmably selectable variable sized protected address range within said memory device by hardware configuration;

preventing software reconfiguration of said protected address range;

decoding the address range defined by said defining step and generating a memory protect signal corresponding to the predetermined protected address range;

gating the memory protect signal of said decoding step with a write control signal associated with the programmable memory device to inhibit WRITES to said protected address range in said programmable memory device while enabling data in the protected address range to be read; and

disabling said gating step to prevent said WRITE inhibit to said memory, said disabling step allowing data to be read and written to said memory device.

18. A method in accordance with claim 17 wherein said defining step further comprises the step of wiring a code indicative of the predetermined addressable data stored in the programmable memory.

19. A method in accordance with claim 18 wherein the decoding step further comprises the step of comparing addresses at the programmable memory with addresses defmed according to said code.

20. A method in accordance with claim 19, wherein said comparing step compares upper address bits for defining addresses in an upper address space.

21. An apparatus for protecting a predetermined readable and programmable address range in a readable and programmable memory device, said apparatus comprising:

means for defining a predetermined protected address range in said memory device with hardware, said defining means corresponding to said predetermined readable and writable address range, wherein said predetermined readable and writable address range may be of a predetermined selectable variable size and adapted to be physically configurable in hardware;

means for preventing software reconfiguration of said protected range;

means responsive to said defining means for decoding addresses corresponding to said predetermined protected address range in said memory device and generating a decode signal when the address signal applied corresponds to said protected addresses;

means responsive to said decoding means for preventing WRITES of said programmable memory device for addresses corresponding to said protected address range in said memory device while enabling data in said protected address range in said memory device to be read;

means for intercepting and disabling erase commands to said memory device for preventing erasure of data in said programmable device; and

means for programmably disabling said WRITES preventing means, said programmably disabling means including means for allowing reads and writes to said protected address range in said memorv device.

22. A computer system comprising:

an address bus, a data bus and a control bus for coupling predetermined devices in the computer system;

a readable and programmable memory device coupled to said address bus having a predetermined amount of storage space defining a predetermined readable and programmable address range;

means coupled to said address bus, said data bus and said control bus for selectively generating address signals and WRITE commands to said memory device; and

means coupled to said address bus and said control bus for decoding addresses on said address bus and disabling WRITE commands for addresses which correspond to a predetermined portion of said predetermined address range in said memory device while enabling data in said predetermined portion of said predetermined address range in said memory device to be read, said disabling means including means for physically configuring in hardware said predetermined portion of said predetermined address range to be of a predetermined selectable variable size and for disabling software reconfiguration of said protected address range, said disabling means further including means for disabling predetermined erase commands to said memory device for preventing erasure of the contents of said memory device; and

means for programmably disabling said decoding and disabling means for allowing reads and writes to said protected address range in said memory device.