Microcontroller with programmable embedded flash memory

• US 6,009,496 A
• Filed: 12/30/1997
• Issued: 12/28/1999
• Est. Priority Date: 10/30/1997
• Status: Expired due to Fees

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Tsai, Hsi-Jung
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/000,959
• Time in Patent Office: 728 Days
• Field of Search: 711/103, 365/189.05, 365/185.09, 365/185.11, 712/37, 712/38, 713/600
• US Class Current: 711/103
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

An architecture for microcontroller with embedded flash memory is provided. The microcontroller allows the reprogramming of data into the embedded flash memory of the microcontroller to be performed on-board without having to dismount the entire IC package of the microcontroller from the circuit board and then use a dedicated writer to perform the write operation. The reprogramming operation can be initiated either by an external reprogramming-enable signal or an internal reprogramming-enable signal. When either of these two signals is generated, it causes an OR gate to output a high-voltage logic signal to a multiplexer to thereby cause the multiplexer to select a ROM unit for connection to the microprocessor unit. This allows the microprocessor unit to execute a reprogramming control routine stored in the ROM unit. The flash memory unit further stores a reprogramming detection/initialization routine which checks whether a flash reprogramming request signal is issued from the main-unit interface. With this microcontroller architecture, the reprogramming of data into the embedded flash memory can be performed on-board without having to laboriously dismount the microcontroller from the circuit board. The reprogramming operation is therefore quite easy and quick to perform, thus more cost-effective than the prior art.

Claims

1. A microcontroller coupled to a main-unit interface, which comprises:

a microprocessor unit coupled via an external data bus to said main-unit interface, said microprocessor unit generating an internal reprogramming-enable signal and a set of latch-enable signals for control of data transfer during a reprogramming operation;

a ROM unit used to store a reprogramming control routine therein;

a flash memory unit used to store a main control program for execution by said microprocessor unit to perform a control function specific to said microcontroller;

an external jumper being manually set to generate an external reprogramming-enable signal;

an OR gate coupled to said microprocessor unit and said external jumper for generating a selection signal when either of said internal reprogramming-enable signal and said external reprogramming-enable signal is present;

a multiplexer having two input ends respectively connected to the data buses of said ROM unit and said flash memory unit and one output end connected to the data bus of said microprocessor unit, said multiplexer selecting said ROM unit for connection to said microprocessor unit when said selection signal from said OR gate is present, and selecting said flash memory unit otherwise; and

a latch buffer coupled between said flash memory unit and said microprocessor unit, said latch buffer being under control in response to the latch-enable signals from said microprocessor unit for data transfer between said flash memory unit and said microprocessor unit;

wherein the generation of either of said internal reprogramming-enable signal and said external reprogramming-enable signal causes said multiplexer to select the ROM unit for connection to the microprocessor unit, causing the microprocessor unit to execute said reprogramming control routine stored in said ROM unit to control a reprogramming operation to write data into said flash memory unit.

2. The microcontroller of claim 1, wherein said external jumper is switchable between a system voltage and a ground voltage in such a manner that when said external jumper is switched to the system voltage, the external reprogramming-enable signal is triggered to generate.

3. The microcontroller of claim 2, wherein the external reprogramming-enable signal from said external jumper causes said multiplexer to select the ROM unit for connection to the microprocessor unit, causing the microprocessor unit to execute said reprogramming control routine stored in said ROM unit to control a reprogramming operation to write data into said flash memory unit.

4. The microcontroller of claim 1, wherein said flash memory unit further stores a reprogramming detection/initialization routine which is executed by said microprocessor unit to detect whether a flash-reprogramming request signal is issued from said main-unit interface.

5. The microcontroller of claim 1, wherein said reprogramming control routine stored in said ROM unit is used to control said microprocessor unit to receive the data to be reprogrammed into said flash memory unit from said main-unit interface.

6. The microcontroller of claim 5, wherein said data to be reprogrammed into said flash memory unit include a data signal, an address signal, and a control signal.

7. The microcontroller of claim 6, wherein said latch buffer comprises:

a first latch, in response to a first latch-enable signal from said microprocessor unit, for latching the address signal on a data bus connected to said flash memory unit;

a second latch, in response to a second latch-enable signal from said microprocessor unit, for latching a flash read/write request signal on a signal line connected to said flash memory unit; and

a transceiver coupled between said flash memory unit and said microprocessor unit;

said transceiver operating in response to a transmission/reception control signal in such a manner that during a write operation, said transmission/reception control signal setting said transceiver to a transmission mode, causing said transceiver to transfer the data signal received by said microprocessor unit from said main-unit interface to said flash memory unit; and

during a read operation, said transmission/reception control signal setting said transceiver to a reception mode, causing said transceiver to transfer the data read from said flash memory unit to said microprocessor unit.

8. A microcontroller coupled to a main-unit interface, which comprises:

a microprocessor unit coupled via an external data bus to said main-unit interface, said microprocessor unit generating an internal reprogramming-enable signal and a set of latch-enable signals for control of data transfer during a reprogramming operation;

a ROM unit used to store a reprogramming control routine therein;

a flash memory unit used to store a main control program for execution by said microprocessor unit to perform a control function specific to said microcontroller;

a multiplexer having two input ends respectively connected to the data buses of said ROM unit and said flash memory unit, said multiplexer selecting said ROM unit for connection to said microprocessor unit when said internal reprogramming-enable signal from said microprocessor unit is present, and selecting said flash memory unit otherwise; and

a latch buffer coupled between said flash memory unit and said microprocessor unit, said latch buffer being under control in response to the latch-enable signals from said microprocessor unit for data transfer between said flash memory unit and said microprocessor unit;

wherein the generation of said internal reprogramming-enable signal from said microprocessor unit causes said multiplexer to select the ROM unit for connection to the microprocessor unit, causing the microprocessor unit to execute said reprogramming control routine stored in said ROM unit to control a reprogramming operation to write data into said flash memory unit.

9. The microcontroller of claim 8, wherein said reprogramming control routine stored in said ROM unit is used to control said microprocessor unit to receive the data to be reprogrammed into said flash memory unit from said main-unit interface.

10. The microcontroller of claim 8, wherein said reprogramming control routine stored in said ROM unit is used to control said microprocessor unit to receive the data to be reprogrammed into said flash memory unit from said main-unit interface.

11. The microcontroller of claim 10, wherein said data to be reprogrammed into said flash memory unit include a data signal, an address signal, and a control signal.

12. The microcontroller of claim 8, wherein said latch buffer comprises:

a first latch, in response to a first latch-enable signal from said microprocessor unit, for latching the address signal on a data bus connected to said flash memory unit;

a second latch, in response to a second latch-enable signal from said microprocessor unit, for latching a flash read/write request signal on a signal line connected to said flash memory unit; and

a transceiver coupled between said flash memory unit and said microprocessor unit;

said transceiver operating in response to a transmission/reception control signal in such a manner that during a write operation, said transmission/reception control signal setting said transceiver to a transmission mode, causing said transceiver to transfer the data signal received by said microprocessor unit from said main-unit interface to said flash memory unit; and

during a read operation, said transmission/reception control signal setting said transceiver to a reception mode, causing said transceiver to transfer the data read from said flash memory unit to said microprocessor unit.