Attachment or integration of a BIOS device into a computer system using the system memory data bus

• US 6,009,522 A
• Filed: 09/30/1997
• Issued: 12/28/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Mei California, Inc. (Micron Technology, Inc.)
• Original Assignee: Micro Electronics Incorporated
• Inventors: Klein, Dean A.
• Primary Examiner(s): Palys, Joseph E.
• Assistant Examiner(s): Mai, Rijue
• Application Number:
  US08/941,619
• Time in Patent Office: 819 Days
• Field of Search: 395/652, 395/309, 395/187.01, 365/230, 364/200, 713/1, 713/2, 713/100, 712/33, 710/23, 710/101, 710/104, 710/107, 710/123, 710/128, 710/126
• US Class Current: 713/2
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

Chipset or core logic for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (e.g., the system memory data bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Claims

1. A computer comprising:

a central processing unit;

a system memory bus that includes a system memory data bus;

a BIOS device that is connected to the system memory data bus; and

core logic connecting the central processing unit to the system memory bus comprising;

a state machine for initiating system memory bus cycles in a normal mode; and

logic for bypassing the state machine when a BIOS access is initiated;

wherein the core logic is configured such that if a BIOS access is initiated;

the core logic becomes master of the system memory bus;

a system memory bus cycle in normal mode is not initiated; and

the core logic places the address of the BIOS device on the system memory bus.

2. The computer of claim 1, further comprising:

system memory that is connected to the core logic, wherein the core logic controls memory operations involving the central processing unit and the system memory.

3. The computer of claim 2, wherein the core logic is configured to control BIOS operations involving the central processing unit and the BIOS device on the system memory bus by

decoding signals on the system memory bus,

allowing any other operations involving the system memory bus to be completed,

presenting an address to the BIOS device by placing the address on the system memory data bus,

receiving data stored in the BIOS device at the address by sampling a portion of the system memory data bus, and

transferring the data to the central processing unit.

4. The computer of claim 3, wherein the core logic sequences a plurality of low-order bits on the address so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

5. The computer of claim 4, wherein the core logic transfers at least some of the contents of the BIOS device to faster memory at system start-up.

6. The computer of claim 5, wherein the address presented to the ROM BIOS and the data read from the BIOS device occupy different portions of the system memory data bus.

7. The computer of claim 6, wherein the BIOS device is implemented by a non-volatile, electrically-erasable, programmable read-only memory device.

8. The computer of claim 7, wherein eight-bit data units are stored in an eighteen-bit address space within the non-volatile, electrically-erasable, programmable read-only memory device.

9. Core logic that controls BIOS operations in a computer system having a system memory bus, wherein the system memory bus includes a system memory data bus, wherein the BIOS operations involve a central processing unit and a BIOS device that is on the system memory bus, the core logic comprising:

logic for communicating with the central processing unit;

logic for connecting to the system memory bus;

logic for initiating system memory bus cycles;

logic that bypasses the logic for initiating system memory bus cycles when the BIOS device is accessed;

logic that decodes signals on the system memory bus;

logic that presents an address to the BIOS device by placing the address on the system memory data bus;

logic that receives data stored in the BIOS device at the address by sampling a portion of the system memory data bus; and

logic that transfers the data to the central processing unit.

10. The core logic of claim 9, further comprising logic for sequencing a plurality of low-order bits on the address presented to the BIOS device so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

11. The core logic of claim 10, further comprising logic that transfers at least some of the contents of the BIOS device to faster memory at system start-up.

12. Core logic for controlling BIOS operations in a computer system having a central processing unit and a system memory bus, wherein the BIOS operations involve the transfer of data to the central processing unit from a BIOS device on the system memory bus, and wherein the system memory bus includes a system memory data bus;

the core logic comprising;

means operably connected to the central processing unit and the system memory bus for decoding a BIOS operation;

means for initiating system memory bus cycles;

means for presenting an address to the BIOS device by placing the address on the system memory data bus;

means for bypassing the system memory bus cycles when the BIOS device is accessed;

means for receiving data stored in the BIOS device at the address by sampling a portion of the system memory data bus; and

means for transferring the data to the central processing unit.

13. The core logic of claim 12, further comprising hardware for sequencing a plurality of low-order bits on the address presented to the BIOS device so that data from more than one addressable location is read from the BIOS device before the data is transferred to the central processing unit.

14. The core logic of claim 13, further comprising means for transferring at least some of the contents of the BIOS device to faster memory at system start-up.