Method for using fuse identification codes for masking bad bits on memory modules

• US 6,009,536 A
• Filed: 09/20/1996
• Issued: 12/28/1999
• Est. Priority Date: 09/20/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micro Electronics Incorporated
• Inventors: Rohwer, Paul W.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Elmore, Stephen C.
• Application Number:
  US08/716,947
• Time in Patent Office: 1,194 Days
• Field of Search: 395/182.06, 395/181, 365/200, 371/21.1, 371/21.6, 371/22.1
• US Class Current: 714/6.13
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: H01L 2223/5444 for electrical read out

Abstract

A new method for masking off failing memory locations on a Single In-line Memory Module (SIMM) involves reading out identification (ID) codes fused in individual DRAMs. The ID codes are used to index stored fail maps taken from the DRAMs prior to their assembly onto a SIMM. After all failing locations of all of the DRAMs located on a single SIMM are determined, the SIMM is then programmed to re-route these locations to auxiliary memory located on the SIMM.

Claims

1. A method of programming a circuit board comprising a memory device having a plurality of memory locations and a machine-readable identification code, said method comprising:

(a) performing a component-level test to identify one or more failed memory locations and creating a fail map which identifies the one or more failed memory locations;

(b) reading the identification code from the selected memory device;

(c) storing the fail map and the identification code in a storage device;

(d) assembling the memory device onto the circuit board;

(e) reading the identification code for a memory device assembled on the circuit board;

(f) retrieving the fail map for the memory device from the storage device using the read identification code as an index to locate the fail map; and

(g) programming the circuit board to reroute memory access requests away from the one or more failed memory locations, as revealed by the fail map, to one or more corresponding replacement memory locations on the circuit board.

2. The method of claim 1, further comprising repeating the operations described in subparagraphs (a) through (c) of claim 1 at different operating temperatures prior to performing the operations described in subparagraphs (d) through (g) of that claim.

3. The method of claim 1, further comprising repeating the operations described in subparagraphs (a) through (c) of claim 1 in different operating modes prior to performing the operations described in subparagraphs (d) through (g) of that claim.

4. A method of testing a plurality of memory devices for assembly onto a circuit board, each memory device having a plurality of memory locations and a machine-readable identification code, said method comprising:

(a) for each of said plurality of memory devices;

(1) performing a component-level test of the memory device to identify zero or more failed memory locations and creating a fail map in a storage device to identify the zero or more failed memory locations;

(2) reading the identification code for the memory device;

(3) associating the fail map and the identification code in a record in a database stored in a storage device;

(4) repeating the operations described in subparagraphs (a)(1) through (a)(3) at a variety of temperatures and operating modes;

(b) assembling said plurality of memory devices onto the circuit board;

(c) for each of said plurality of memory devices;

(1) reading the identification code for said memory device;

(2) retrieving from the database the fail map associated with the identification code;

(3) determining from the fail map whether one or more failed memory locations exists in the memory device, and if so, then programming the circuit board to reroute memory access requests away from at least one of the failed memory locations to at least one corresponding replacement memory locations on the circuit board.

5. The method of claim 4, wherein at least one of the plurality of memory devices is a DRAM.

6. The method of claim 4, wherein the circuit board comprises a plurality of memory devices, and further comprising repeating operations (a) through (c) for each of the plurality of memory devices prior to installing the memory devices on the circuit board.

7. The method of claim 4, wherein the storage device is a computer.

8. The method of claim 7, wherein the computer executes a database program.

9. A method of using a SIMM test head and a storage device, comprising:

(a) sending an ID code from the SIMM test head to a storage device;

(b) send a fail map from the storage device to the SIMM test head using the ID code as an index to locate the fail map;

(c) converting the fail map into a programming signal; and

(d) programming a SIMM using the programming signal.