Method of making a printed circuit board having filled holes

• US 6,009,620 A
• Filed: 07/15/1998
• Issued: 01/04/2000
• Est. Priority Date: 07/15/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lyjak, Kenneth S., Bhatt, Ashwinkumar C., Welsh, John A., Kotylo, Joseph A., Rai, Amarjit S.
• Primary Examiner(s): Young, Lee
• Assistant Examiner(s): Rushing, Jr., Bobby
• Application Number:
  US09/115,715
• Time in Patent Office: 538 Days
• Field of Search: 29/830, 29/840, 29/846, 29/847, 29/852, 427/97
• US Class Current: 29/852
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2203/0278 Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
• CPC Class Codes: H05K 3/0094 Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method of making a circuitized substrate wherein fill material is forced into the substrate'"'"'s holes to thus provide additional support for conductive circuitry or the like thereon, thus increasing the final product'"'"'s circuit density. The fill is provided in a substantially uncured state, following which partial cure occurs. Thereafter, the fill is substantially fully cured and the aforementioned circuit elements may then be provided directly thereon. Alternatively, a dual fill process is used with both quantities of uncured fill being disposed in each hole and then cured by a singular UV exposure step.

Claims

1. A method of making a circuitized substrate, said method comprising:

providing a layer of dielectric material having a first surface;

forming at least one hole within said layer of dielectric material;

positioning a quantity of uncured, dielectric fill material within said at least one hole and onto at least part of said first surface;

partially curing said quantity of uncured, dielectric fill material within said at least one hole;

removing said dielectric fill material on said at least part of said first surface; and

thereafter further curing said partially cured dielectric fill material within said at least one hole.

2. The method of claim 1 wherein said layer of dielectric material is formed as a laminate.

3. The method of claim 1 wherein said at least one hole is formed in said layer of dielectric material using a process selected form the group of processes consisting of drilling, punching, laser ablation and etching.

4. The method of claim 1 wherein said at least one hole within said layer of dielectric material is defined by internal walls within said dielectric material, said method further including the step of forming an electrically conductive layer on said internal walls of said at least one hole within said layer of dielectric material prior to said positioning of said quantity of uncured, dielectric fill material within said at least one hole.

5. The method of claim 4 further including forming said conductive layer onto said at least part of said first surface.

6. The method of claim 5 wherein said electrically conductive layer is formed using an electroless plating operation.

7. The method of claim 1 wherein said quantity of uncured, dielectric fill material is positioned within said at least one hole using a vacuum lamination process.

8. The method of claim 7 wherein said vacuum lamination process is performed at a temperature within the range of about 140°

F. to about 200°

F.

9. The method of claim 1 wherein said partially curing of said dielectric fill material is accomplished using a photoimaging process.

10. The method of claim 9 wherein said photoimaging process comprises exposing said dielectric fill material to UV radiation.

11. The method of claim 10 wherein said exposing of said dielectric fill material is accomplished for a time period of about 30 seconds to about 5 minutes.

12. The method of claim 9 wherein said removing of said dielectric fill material from said at least one part of said first surface is accomplished using photoimaging processing.

13. The method of claim 1 wherein a portion of said uncured fill material extends substantially above said first surface following said removing of said fill material on said at least part of said first surface.

14. The method of claim 13 wherein said portion extending substantially above said first surface is removed using a mechanical removal process.

15. The method of claim 1 wherein said further curing of said partially cured dielectric fill material is accomplished using a photoimaging process.

16. The method of claim 15 wherein said photoimaging process comprises exposing said partially cured dielectric fill material to UV radiation.

17. The method of claim 16 wherein said exposing of said partially cured dielectric fill material is accomplished for a time period of about 30 seconds to about 5 minutes and is followed by a baking step wherein the fill material is heated to a temperature of from about 250°

F. to about 400°

F.

18. The method of claim 1 further including applying an electrically conductive layer on said dielectric fill material after said further curing thereof.

19. The method of claim 18 further including electrically coupling at least one electrical component to said electrically conductive layer on said dielectric fill material.

20. The method of claim 1 further including positioning at least one electrical component on said first surface and substantially over said at least one hole, and thereafter providing a quantity of encapsulant material substantially under said electrical component, said fill material within said at least one hole preventing passage of said encapsulant material through said at least one hole.

21. A method of making a circuitized substrate, said method comprising:

providing a layer of dielectric material having a first surface;

forming at least one hole within said layer of dielectric material;

positioning a first quantity of uncured, dielectric fill material within said at least one hole and onto at least part of said first surface;

removing said uncured, dielectric fill material on said at least part of said first surface;

positioning a second quantity of uncured, dielectric fill material onto said first surface and substantially over said at least one hole having said first quantity of uncured, dielectric fill material therein; and

thereafter substantially curing said first quantity of uncured dielectric fill material within said at least one hole and said second quantity of dielectric fill material within and substantially over said at least one hole.

22. The method of claim 21 wherein said layer of dielectric material is formed as a laminate.

23. The method of claim 21 wherein said at least one hole is formed in said layer of dielectric material using a process selected from the group of processes consisting of drilling, punching, laser ablation and etching.

24. The method of claim 21 wherein said at least one hole within said layer of dielectric material is defined by internal walls within said dielectric material, said method further including the step of forming an electrically conductive layer on said internal walls of said at least one hole within said layer of dielectric material prior to said positioning of said first quantity of uncured, dielectric fill material within said at least one hole.

25. The method of claim 24 further including forming said conductive layer onto said at least part of said first surface.

26. The method of claim 25 wherein said electrically conductive layer is formed using an electroless plating operation.

27. The method of claim 21 wherein said first and second quantities of uncured, dielectric fill material are positioned within and substantially over said at least one hole using a vacuum lamination process.

28. The method of claim 27 wherein said vacuum lamination process is performed at a temperature within the range of about 140°

F. to about 200°

F.

29. The method of claim 21 wherein said substantially curing of said dielectric fill material is accomplished using a photoimaging process.

30. The method of claim 29 wherein said photoimaging process comprises exposing said dielectric fill material to UV radiation.

31. The method of claim 30 wherein said exposing of said dielectric fill material is accomplished for a time period of about 30 seconds to about five minutes.

32. The method of claim 21 further including applying an electrically conductive layer on said second quantity of said dielectric fill material after said curing thereof.

33. The method of claim 32 further including electrically coupling at least one electrical component to said electrically conductive layer on said dielectric fill material.

34. The method of claim 21 further including positioning at least one electrical component on said first surface and substantially over said at least one hole, and thereafter providing a quantity of encapsulant material substantially under said electrical component, said fill material within said at least one hole preventing passage of said encapsulant material through said at least one hole.