Reduction of dislocations in a heteroepitaxial semiconductor structure

• US 6,010,937 A
• Filed: 09/05/1995
• Issued: 01/04/2000
• Est. Priority Date: 09/05/1995
• Status: Expired due to Term

• Current Assignee: Masimo Semiconductor Inc. (Masimo Corporation)
• Original Assignee: Spire Corporation
• Inventors: Wojtczuk, Steven J., Karam, Nasser H.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Berry, Renee R.
• Application Number:
  US08/523,694
• Time in Patent Office: 1,582 Days
• Field of Search: 438/798, 438/930, 438/935, 438/363, 438/413, 438/495, 117/95, 117/84, 117/104
• US Class Current: 438/363
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02461 Phosphides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02617 Deposition types
• CPC Class Codes: H01L 31/0693 the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
• CPC Class Codes: H01L 31/1852 comprising a growth substrate not being an AIIIBV compound
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

A heteroepitaxial semiconductor device having reduced density of threading dislocations and a process for forming such a device. According to one embodiment, the device includes a substrate which is heat treated to a temperature in excess of 1000° C., a film of arsenic formed on the substrate at a temperature between 800° C. and 840° C., a GaAs nucleation layer of less than 200 angstroms and formed at a temperature between about 350° C. and 450° C., and a plurality of stacked groups of layers of InP, wherein adjacent InP layers are formed at different temperatures.

Claims

1. A heteroepitaxial semiconductor device comprising:

a substrate formed from a first semiconductor material;

a plurality of stacked groups of layers of a second semiconductor material formed on said substrate, wherein adjacent layers within each group of layers are formed at different temperature ranges to induce mechanical stresses and, thereby, reduce dislocations.

2. A device according to claim 1 wherein said temperature ranges at which said layers in each group of layers are formed define a temperature profile, and said temperature profile repeats in each adjacent stacked groups of layers.

3. A device according to claim 1 wherein each said stacked groups includes a stacked pair of layers and wherein each of said stacked pairs of layers comprises a first epitaxial layer of said second semiconductor material having a first thickness and formed at a first temperature range, and a second epitaxial layer of said second semiconductor material having a second thickness and formed at a second temperature range.

4. A device according to claim 3 wherein said first temperature range and said second temperature range define a temperature profile within each of said stacked pairs, and said temperature profile repeats for each adjacent stacked pair of layers.

5. A device according to claim 3 wherein said first thickness and said second thickness define a thickness profile within each of said stacked pairs, and said thickness profile repeats for each adjacent stacked pair of layers.

6. A device according to claim 3 wherein said first temperature range is less than said second temperature range.

7. A device according to claim 3 wherein said first temperature range is greater than said second temperature range.

8. A device according to claim 3 wherein in said first thickness is substantially equal to said second thickness.

9. A device according to claim 3 wherein said first thickness is greater than said second thickness.

10. A device according to claim 3 wherein said first thickness is less than said second thickness.

11. A device according to claim 3 wherein said first temperature range is between about 575°

C. and about 625°

C.

12. A device according to claim 3 wherein said second temperature range is between about 650°

C. and about 725°

C.

13. A device according to claim 1 further comprising an epitaxial semiconductor device formed on an uppermost one of said stacked groups of layers.

14. A device according to claim 13 wherein said epitaxial semiconductor device comprises a photovoltaic cell.

15. A device according to claim 14 wherein said photovoltaic cell comprises,

a p-type doped layer of a semiconductor compound formed on said uppermost stacked group;

and

an n-type doped layer of said semiconductor compound formed on said p-type doped layer;

wherein said semiconductor compound is selected from periodic table group III-V and group II-VI compounds.

16. A device according to claim 14 further comprising a tunnel junction formed between said photovoltaic cell and said substrate.

17. A device according to claim 16 wherein said tunnel junction comprises,

a first layer of InGaAs having a selected doping type and formed on said uppermost stacked group of layers;

and

a second layer of InGaAs having a doping type opposite to said first doping type and formed on said first layer of InGaAs.

18. A device according to claim 16 wherein said tunnel junction comprises,

an n-type doped layer of InGaAs formed on said uppermost stacked group of layers;

and

a p-type doped layer of InGaAs formed on said n-type doped layer of InGaAs.

19. A device according to claim 14 wherein said photovoltaic cell comprises,

a first epitaxial layer of InP having a first doping type and formed on said uppermost stacked group of layers;

and

a second substantially single crystal layer of InP having a doping type opposite to said first doping type and formed on said first epitaxial layer of InP.

20. A device according to claim 1 wherein said plurality of stacked groups of layers comprises a plurality of stacked groups of epitaxial layers of a semiconductor compound, and said device further comprises a photovoltaic cell having at least one further layer of said semiconductor compound, wherein said semiconductor compound is selected from periodic table group III-V and group II-VI compounds.

21. A device according to claim 1 wherein said plurality of stacked groups of layers comprises a plurality of stacked groups of epitaxial layers of a semiconductor compound, wherein said semiconductor compound is selected from periodic table group III-V and group II-VI compounds.

22. A device according to claim 21 wherein said epitaxial layers have the same doping type.

23. A device according to claim 21 wherein said semiconductor compound is InP.

24. A device according to claim 23 wherein said first and second epitaxial layers have the same doping type.

25. A device according to claim 1 wherein said plurality of stacked groups of layers comprises a plurality of stacked groups of epitaxial layers of a group II-VI compound.

26. A device according to claim 1 wherein said substrate is Si.

27. A device according to claim 1 further comprising a nucleation layer formed between said substrate and a first one of said stacked groups of layers.

28. A device according to claim 27 wherein said nucleation layer is formed from GaAs.

29. A device according to claim 27 wherein said nucleation layer has a thickness of less than about 200 angstroms.

30. A device according to claim 27 wherein said substrate is heat treated at a temperature in excess of about 1000°

C.

31. A device according to claim 27 further comprising a film of arsenic formed between said nucleation layer and said substrate.

32. A device according to claim 31 wherein said film of arsenic is formed at a temperature between about 800°

C. and about 840°

C.

33. A device according to claim 27 wherein said nucleation layer comprises a GaAs layer of less than about 200 angstroms.

34. A device according to claim 33 wherein said nucleation layer is formed on said substrate at a temperature between about 350°

C. and about 450°

C.

35. A device according to claim 27 wherein said substrate is heat treated to a temperature in excess of about 1000°

C., and wherein said nucleation layer comprises a GaAs layer of less than about 200 angstroms formed at a temperature between about 350°

C. and about 450°

C., said device further comprising a film of arsenic formed between said nucleation layer and said substrate at a temperature between about 800°

C. and about 840°

C.

36. A device according to claim 23 wherein said substrate is a Si substrate.