Flash memory cell with vertical channels, and source/drain bus lines

• US 6,011,288 A
• Filed: 12/22/1997
• Issued: 01/04/2000
• Est. Priority Date: 12/22/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chrong-Jung, Chen, Shui Hung, Kuo, Di-Son, Chen, Jong
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/995,999
• Time in Patent Office: 743 Days
• Field of Search: 257/315, 257/316, 257/317, 257/321
• US Class Current: 257/321
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A vertical memory device on a silicon semiconductor substrate comprises a floating gate trench in the substrate, in the array, the trench. The walls of the floating gate trench were doped with a threshold implant through the trench surfaces. There is a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. There is a floating gate electrode in the trench on the outer surfaces of the tunnel oxide layer. There are source/drain regions in the substrate self-aligned with the floating gate electrode. The source line and a drain line form above the source region and the drain region respectively. An interelectrode dielectric layer overlies the top surface of the floating gate electrode, and the source line and the drain line, and there is a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Claims

1. A vertical memory device on a silicon semiconductor substrate comprising:

a floating gate trench in said silicon semiconductor substrate, said trench having trench surfaces, said trench having a depth from about 100 Å

to about 20,000 Å

,

the walls of said floating gate trench doped with a threshold implant through said trench surfaces,

a tunnel oxide layer on said trench surfaces, said tunnel oxide layer having outer surfaces, said tunnel oxide layer having a thickness from about 70 Å

to about 200 Å

,

a floating gate electrode in said trench on said outer surfaces of said tunnel oxide layer,

said floating gate electrode comprises doped polysilicon with a thickness from about 1,000 Å

to about 3,000 Å

,

source/drain regions in said substrate self-aligned with said floating gate electrode,

said source/drain regions were implanted with a dopant selected from the group consisting of arsenic and phosphorus with a concentration of from about 1 E 14 atoms/cm³ to about 1 E 16 atoms/cm³,

a source line region is provided on the source side of said trench aligned with and over said source region,

a drain line region is provided on the drain side of said trench aligned with and over said drain region,

an interelectrode dielectric layer over the top surface of said floating gate electrode, and said source line and said drain line, and

a control gate electrode over said interelectrode dielectric layer over the top surface of said floating gate electrode.