Field programmable gate array with dedicated computer bus interface and method for configuring both

• US 6,011,407 A
• Filed: 06/13/1997
• Issued: 01/04/2000
• Est. Priority Date: 06/13/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: New, Bernard J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/876,909
• Time in Patent Office: 935 Days
• Field of Search: 326/37-41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources

Abstract

A field programmable gate array is provided which has a programmable portion and a dedicated controller-interface circuit. The programmable portion includes conventional input/output (I/O) blocks and configurable logic blocks (CLBs). The controller-interface circuit allows the FPGA to be operably coupled to an external computer bus, such as a PCI bus. The programmable portion and the controller-interface circuit are separately programmable. As a result, after the controller-interface circuit is initialized, the programmable portion can be cleared and reconfigured without having to re-initialize the controller-interface circuit. The programmable portion is programmed in accordance with an implied addressing scheme in response to a configuration bit stream.

Claims

1. A field programmable gate array (FPGA) comprising:

a dedicated bus controller-interface circuit for connecting to an external computer bus; and

a programmable portion coupled to the bus controller-interface circuit, wherein the programmable portion is programmable by implied addressing to implement a logic circuit which is operably coupled to the external computer bus through the controller-interface circuit, wherein the dedicated bus controller-interface circuit and the programmable portion are separately programmable.

2. The FPGA of claim 1, wherein the external computer bus is a PCI bus.

3. The FPGA of claim 1, wherein the programmable portion is programmable from the external computer bus.

4. The FPGA of claim 1, further comprising a programming circuit coupled to receive a parallel configuration bit stream from the external computer bus, said programming circuit providing a configuration data stream in response to the parallel configuration bit stream, wherein the programmable portion is configured in response to the configuration data stream.

5. The FPGA of claim 1, wherein the programmable portion comprises:

a plurality of input/output (I/O) blocks; and

an array of configurable logic blocks (CLBs) coupled to the I/O blocks.

6. The FPGA of claim 4, wherein the programming circuit further comprises an output terminal which routes the configuration data stream out of the FPGA, thereby allowing additional FPGAs to be programmed in a daisy-chained manner from the external computer bus.

7. The FPGA of claim 4, wherein the programming circuit comprises a parallel-to-serial converter which converts the parallel configuration bit stream to a serial configuration bit stream which forms the configuration data stream.

8. A field programmable gate array (FPGA) comprising:

a dedicated bus controller-interface circuit for connecting to an external computer bus; and

a programmable portion coupled to the bus controller-interface circuit, wherein the programmable portion is programmable by implied addressing to implement a logic circuit which is operably coupled to the external computer bus through the controller-interface circuit, wherein the dedicated bus controller-interface circuit and the programmable portion are separately programmable, and wherein the bus controller-interface circuit comprises;

a receive first in, first out (FIFO) memory coupled between the external computer bus and the programmable portion;

a transmit FIFO memory coupled between the external computer bus and the programmable portion;

a state machine for controlling the receive and transmit FIFO memories, the state machine being coupled to the receive FIFO memory, the transmit FIFO memory, the programmable portion and the external computer bus; and

a configuration memory coupled to the external computer bus, the configuration memory being programmable to configure the bus controller-interface circuit.

9. A method of operating a field programmable gate array (FPGA) comprising a dedicated bus controller-interface circuit and a programmable portion coupled to the bus controller-interface circuit, the method comprising the steps of:

initializing the dedicated bus controller-interface circuit to enable the bus controller-interface circuit to be operably coupled to an external bus; and

then

independently programming the configuration of the programmable portion using an implied addressing scheme.

10. The method of claim 9, wherein the step of programming the programmable portion further comprises the step of providing a configuration bit stream from the external computer bus to the programmable portion.

11. The method of claim 9, further comprising the steps of:

receiving a parallel configuration bit stream from the external computer bus; and

programming the configuration of the programmable portion in response to the parallel configuration bit stream.

12. The method of claim 11, further comprising the steps of:

serializing the parallel configuration bit stream into a serial configuration bit stream; and

providing the serial configuration bit stream to the programmable portion.

13. The method of claim 12, further comprising the steps of:

routing the serial configuration bit stream out of the FPGA;

programming additional FPGAs in a daisy-chained manner in response to the serial configuration bit stream.