Transmission-line loss equalizing circuit

• US 6,011,435 A
• Filed: 01/06/1997
• Issued: 01/04/2000
• Est. Priority Date: 06/12/1996
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamagata, Yasutaka, Sakai, Toshiyuki, Murakami, Norio, Takeyabu, Masato
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/778,791
• Time in Patent Office: 1,093 Days
• Field of Search: 330/9, 330/69, 330/252, 330/258, 330/260, 330/310
• US Class Current: 330/252
• CPC Class Codes: H03F 2203/45291 the active amplifying circuit [AAC] comprising balancing means
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45766 by using balancing means

Abstract

A transmission-line loss equalizing circuit includes an equalizer, a gain control circuit for controlling the gain of the equalizer based upon the peak value of an equalized output, a slicer for slicing the equalized output and outputting a data pulse, a timing extraction pulse and an equalization control pulse, a DC feedback level detector for detecting a DC component of the equalized output and feeding the DC component back to the equalizer, and an attenuating circuit provided as an initial stage of the equalizer. A plurality of √fAGC circuits constructing the equalizer are cascade-connected and constructed by a differential non-inverting amplifier.

Claims

1. A differential non-inverting amplifier circuit comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential outputs comprising a non-inverting output terminal and an inverting output terminal; and

a balance level input terminal for deciding average DC levels of said pair of differential outputs,

wherein the non-inverting input terminal, the inverting input terminal, the non-inverting output terminal and the inverting output terminal of said operational amplifier serve as a first signal input terminal, second signal input terminal, first signal output terminal and second signal output terminal, respectively, a first passive element is connected between the inverting feedback input terminal and ground, a second passive element having an impedance equal to that of the first passive element is connected between the non-inverting feedback input terminal and ground, a third passive element is connected between the inverting feedback input terminal and the and the non-inverting output terminal, and a fourth passive element having an impedance equal to that of the third passive element is connected between the non-inverting feedback input terminal and the inverting output terminal.

2. A differential-type variable high-pass filter according to claim 1, said high-pass filter having circuits, each of which is obtained by serially connecting a resistor and a capacitor, as the first and second passive elements of said differential non-inverting amplifier circuit, and variable resistors as the third and fourth passive elements of said differential non-inverting amplifier circuit.

3. The variable high-pass filter according to claim 2, wherein the non-inverting input terminal and inverting input terminal of said operational amplifier serve as differential input terminals, one end of a resistor is connected to the non-inverting output terminal, one end of a resistor having a resistance value equal to that of said first-mentioned resistor is connected to the inverting output terminal of said operational amplifier, other ends of these resistors each serve as a differential output terminal, and a circuit having an impedance value equal to that of the serially connected resistor-capacitor circuit serving as the first or second passive element is provided between said differential output terminals.

4. A transmission-line loss equalizing circuit according to claim 2, wherein said variable high-pass filter is provided as a √

fAGC circuit.

5. A transmission-line loss equalizing circuit according to claim 2, wherein a plurality of said differential variable high-pass filters are cascade-connected inside an integrated circuit, and the first, second, third and fourth passive elements of each differential variable high-pass filter are provided inside the integrated circuit to construct a √

fAGC circuit.

6. A differential voltage follower comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential outputs comprising a non-inverting output terminal and an inverting output terminal; and

a balance level input terminal for deciding average DC levels of said pair of differential outputs,

wherein the non-inverting input terminal of said operational amplifier serves as a non-inverting signal input terminal, the inverted input terminal of said operational amplifier serves as an inverting signal input terminal, the non-inverting output terminal and inverting feedback input terminal of said operational amplifier are short-circuited and serve as a non-inverting signal output terminal, and the inverting output terminal and non-inverting feedback input terminal of said operational amplifier are short-circuited and serve as an inverting signal output terminal.

7. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential outputs comprising a non-inverting output terminal and an inverting output terminal; and

a balance level input terminal for deciding average DC levels of said pair of differential outputs;

a balance signal input means for entering a balance signal;

means for mirroring a sum of currents which flow through non-inverting sides of said two differential input circuits;

means for mirroring a sum of currents which flow through inverting sides of said two differential input circuits;

cascode amplifier stages in which the respective current sums are mirrored;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the cascode amplifier stages;

a differential circuit to which the common mode and the balance signal are input; and

means for mirroring each current, which flows through a non-inverted side and an inverted side of said differential circuit, in each cascode amplifier stage;

output signals of the respective cascode amplifier stages being delivered as a pair of differential output signals of said operational amplifier.

8. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential outputs comprising a non-inverting output terminal and an inverting output terminal;

a balance level input terminal for deciding average DC levels of said pair of differential outputs;

a balance signal input means for entering a balance signal;

means for mirroring a sum of currents which flow through non-inverted sides of said two differential input circuits;

means for mirroring a sum of currents which flow through inverted sides of said two differential input circuits;

cascode amplifier stages in which the respective current sums are mirrored;

two phase compensating means connected to the output of the respective cascode amplifier stages;

two output buffers connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two output buffers;

a differential circuit to which the common mode and the balance signal are input; and

means for mirroring each current, which flows through a non-inverted side and an inverted side of said differential circuit, in each of the two cascode amplifier stages;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

9. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential outputs comprising a non-inverting output terminal and an inverting output terminal;

a balance level input terminal for deciding average DC levels of said pair of differential outputs;

a balance signal input means for entering a balance signal;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said two differential input circuits is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two differential input circuits is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two cascode amplifier stages;

a differential circuit to which the common mode and the balance signal are input;

and means for mirroring each current, which flows through a non-inverted side and an inverted side of said differential circuit, in each of the two cascode amplifier stages;

output signals of the two cascode amplifier stages being delivered as a pair of differential output signals of said operational amplifier.

10. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential outputs comprising a non-inverting inverting output terminal and an inverting output terminal;

a balance level input terminal for deciding average DC levels of said pair of differential outputs;

a balance signal input means for entering a balance signal;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said two differential inputs is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two differential input circuits is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

an output buffer connected to an output of each cascode amplifier stage;

means for detecting a common mode of the two output buffers;

a differential circuit to which the common mode and the balance signal are input; and

means for mirroring each current, which flows through a non-inverted side and an inverted side of said pair of differential circuits, in each of the two cascode amplifier stages;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

11. A differential non-inverting amplifier circuit comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals,

wherein the non-inverting input terminal, the inverting input terminal, the non-inverting output terminal and the inverting output terminal of said operational amplifier serve as a first signal input terminal, second signal input terminal, first signal output terminal and second signal output terminal, respectively, a first passive element is connected between the inverting feedback input terminal and ground, a second passive element having an impedance equal to that of the first passive element is connected between the non-inverting feedback input terminal and ground, a third passive element is connected between the inverting feedback input terminal and the non-inverting output terminal, a fourth passive element having an impedance equal to that of the third passive element is connected between the non-inverting feedback input terminal and the inverting output terminal, a constant voltage level is input to one of the two balance level input terminals and a variable level is input to the other of the two balance level input terminals.

12. A differential-type variable high-pass filter according to claim 11, said high-pass filter having circuits, each of which is obtained by serially connecting a resistor and a capacitor, as the first and second passive elements of said differential non-inverting amplifier circuit, and variable resistors as the third and fourth passive elements of said differential non-inverting amplifier circuit.

13. The variable high-pass filter according to claim 12, wherein the non-inverting input terminal and inverting input terminal of said operational amplifier serve as differential input terminals, one end of a resistor is connected to the non-inverting output terminal, one end of a resistor having a resistance value equal to that of said first-mentioned resistor is connected to the inverting output terminal of said operational amplifier, other ends of these resistors each serve as a differential output terminal, and a circuit having an impedance value equal to that of the serially connected resistor-capacitor circuit serving as the first or second passive element is provided between said differential output terminals.

14. A transmission-line loss equalizing circuit according to claim 12, wherein said variable high-pass filter is provided as a √

fAGC circuit.

15. A transmission-line loss equalizing circuit according to claim 12, wherein a plurality of said differential variable high-pass filters are cascade-connected inside an integrated circuit, and the first, second, third and fourth passive elements of each differential variable high-pass filter are provided inside the integrated circuit to construct a √

fAGC circuit.

16. A differential voltage follower comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals,

wherein the non-inverting input terminal of said operational amplifier serves as a non-inverting signal input terminal, the inverting input terminal of said operational amplifier serves as an inverting signal input terminal, the non-inverting output terminal and

inverting feedback input terminal of said operational amplifier are short-circuited and serve as a non-inverting signal output terminal, and the inverting output terminal and non-inverting feedback input terminal of said operational amplifier are short circuited and serve as an inverting signal output terminal.

17. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non-inverting and inverting balance signals;

means for mirroring a sum of currents which flow through non-inverting sides of said two differential input circuits;

means for mirroring a sum of currents which flow through inverted sides of said two differential input circuits;

cascode amplifier stages in which the respective current sums are mirrored;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two cascode amplifier stages;

a differential circuit to which the common mode and the two non-inverting and inverting balance signals are input;

means for mirroring a current, which flows through a non-inverted side of said differential circuit, on a non-inverted side of said cascode amplifier stages; and

means for mirroring a current, which flows through an inverted side of said differential circuit, on an inverted side of said cascode amplifier stages;

output signals of the two cascode amplifier stages being delivered as a pair of differential output signals of said operational amplifier.

18. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non-inverted and inverted balance signals;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said two differential input circuits is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two differential input circuits is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two cascode amplifier stages;

a differential circuit to which the common mode and the two balance signals are input;

means for mirroring a current, which flows through a non-inverted side of said differential circuit, on a non-inverted side of said cascode amplifier stages; and

means for mirroring a current, which flows through an inverted side of said differential circuit, on an inverted side of said cascode amplifier stages;

output signals of the two cascode amplifier stages being delivered as a pair of differential output signals of said operational amplifier.

19. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal inputs for entering non-inverted and inverted balance signals;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said two differential input circuits is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two differential input circuits is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

two output buffers connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two output buffers;

a differential circuit to which the common mode and the two balance signals are input;

means for mirroring a current, which flows through a non-inverted side of said differential circuit, on a non-inverted side of said cascode amplifier stages; and

means for mirroring a current, which flows through an inverted side of said differential circuit, on an inverted side of said cascode amplifier stages;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

20. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non-inverted and inverted balance signals;

first mirror means for mirroring a sum of currents which flow through non-inverted sides of the two differential input circuits;

second mirror means for mirroring a sum of currents which flow through inverted sides of the two differential input circuits;

a first cascode amplifier stage in which said sum of the current is mirrored by said first mirror means;

a second cascode amplifier stage in which said sum of the current is mirrored by said second mirror means;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode off the two cascode amplifier stages;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second differential common-mode feedback circuit to which the common mode and the inverted balance signal are input;

third mirror means for mirroring a current, which flows through one side of said first differential common-mode feedback circuit, in said first cascode amplifier stage; and

fourth mirror means for mirroring a current, which flows through one side of said second differential common-mode feedback circuit, in said second cascode amplifier stage;

output signals of the two cascode amplifier stages being delivered as a pair of differential output signals of said operational amplifier.

21. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal inputs for entering non-inverted and inverted balance signals;

first mirror means for mirroring a sum of currents which flow through non-inverted sides of the two differential input circuits;

second mirror means for mirroring a sum of currents which flow through inverted sides of the two differential input circuits;

a first cascode amplifier stage in which said sum of the current is mirrored by said first mirror means;

a second cascode amplifier stage in which said sum of the current is mirrored by said second mirror means;

two phase compensating means connected to the output of the respective cascode amplifier stages;

two output buffers connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two output buffers;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second differential common-mode feedback circuit to which the common mode and the inverted balance signal are input;

third mirror means for mirroring a current, which flows through one side of said first differential common-mode feedback circuit, in said first cascode amplifier stage; and

fourth mirror means for mirroring a current, which flows through one side of said second differential common-mode feedback circuit, in said second cascode amplifier stage;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

22. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non inverted and inverted balance signals;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said two differential input circuits is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two differential input circuits is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two cascode amplifier stages;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second differential common-mode feedback circuit to which the common mode and the inverted balance signal are input;

means for mirroring a current, which flows through one side of said first differential common-mode feedback circuit, in one of said cascode amplifier stages; and

means for mirroring a current, which flows through one side of said second pair of differential common-mode feedback circuit, in the other of said cascode amplifier stages;

output signals of the two cascode amplifier stages being delivered as a pair of differential output signals of said operational amplifier.

23. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal inputs for entering non-inverted and inverted balance signals;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said differential input circuit is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two differential input circuits is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

two output buffer connected to the output of the respective cascode amplifier stage;

means for detecting a common mode of the two output buffers;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second differential common-mode feedback circuit to which the common mode and the inverting balance signal are input;

means for mirroring a current, which flows through one side of said first pair of differential common-mode feedback circuit, in one of said cascode amplifier stages; and

means for mirroring a current, which flows through one side of said second differential common-mode feedback circuit, in the other of said cascode amplifier stages;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

24. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non inverted and inverted balance signals;

mirror means for mirroring a sum of currents which flow through non-inverted sides of the two pairs of differential input circuit;

mirror means for mirroring a sum of currents which flow through inverted sides of the two differential input circuit;

two cascode amplifier stages in which the respective current sums are mirrored;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the output of the two cascode amplifier stages;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second differential common-mode feedback circuit to which the common mode and the inverted balance signal are input;

means for folding a current, which flows through one side of said first differential common-mode feedback circuit, in one of said cascode amplifier stages; and

means for folding a current, which flows through one side of said second differential common-mode feedback circuit, in the other of said cascode amplifier stages;

output signals of the two cascode amplifier stages being delivered as a pair of differential output signals of said operational amplifier.

25. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non inverted and inverted balance signals;

mirror means for mirroring a sum of currents which flow through non-inverted sides of the two differential input circuit;

mirror means for mirroring a sum of currents which flow through inverting sides of the two differential input circuit;

two cascode amplifier stages in which the respective current sums are mirrored;

phase compensating means connected to an output of each cascode amplifier stage;

two output buffers connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two output buffers;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second differential common-mode feedback circuit to which the common mode and the inverted balance signal are input;

means for folding a current, which flows through one side of said first differential common-mode feedback circuit, in one of said cascode amplifier stages; and

means for folding a current, which flows through one side of said second differential common-mode feedback circuit, in the other of said cascode amplifier stages;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

26. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non inverted and inverted balance signals;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said two differential input circuit is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two differential input circuit is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the outputs of said two cascode amplifier stages;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second differential common-mode feedback circuit to which the common mode and the inverted balance signal are input;

means for folding a current, which flows through one side of said first differential common-mode feedback circuit, in one of said cascode amplifier stages; and

means for folding a current, which flows through one side of said second differential common-mode feedback circuit, in the other of said cascode amplifier stages;

output signals of the two cascode stages being delivered as a pair of differential output signals of said operational amplifier.

27. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non inverted and inverted balance signals;

a cascode amplifier stage in which a sum of currents which flow through non-inverted sides of said two differential input circuit is current-folded;

a cascode amplifier stage in which a sum of currents which flow through inverted sides of said two pairs of differential input circuit is current-folded;

two phase compensating means connected to the output of the respective cascode amplifier stages;

two output buffers connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two output buffers;

a first differential common-mode feedback circuit to which the common mode and the non-inverted balance signal are input;

a second pair of differential common-mode feedback circuit to which the common mode and the inverted balance signal are input;

means for folding a current, which flows through one side of said first differential common-mode feedback circuit, in one of said cascode amplifier stages; and

means for folding a current, which flows through one side of said second differential common-mode feedback circuit, in the other of said cascode amplifier stages;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

28. An operational amplifier comprising:

two differential input circuits, one circuit comprising a non-inverting input terminal and an inverting feedback input terminal and the other circuit comprising an inverting input terminal and a non-inverting feedback input terminal;

one pair of differential output terminals comprising a non-inverting output terminal and an inverting output terminal;

a first balance level input terminal for deciding an average DC level of a non-inverted output of said pair of differential output terminals;

and a second balance level input terminal for deciding an average DC level of an inverted output of said pair of differential output terminals;

balance signal input means for entering non inverted and inverted balance signals;

means for mirroring a sum of currents which flow through non-inverted sides of said two differential input circuit;

means for mirroring a sum of currents which through inverting sides of said two differential circuit;

two cascode amplifier stages in which the respective current sums are mirrored;

two phase compensating means connected to the output of the respective cascode amplifier stages;

two output buffers connected to the output of the respective cascode amplifier stages;

means for detecting a common mode of the two output buffers;

one differential circuit to which the common mode and the two non-inverted and inverted balance signals are input;

means for mirroring a current, which flows through a non-inverted side of said differential circuit, on a non-inverted side of said cascode amplifier stages; and

means for mirroring a current, which flows through an inverted side of said differential circuit, on an inverted side of said cascode amplifier stages;

output signals of the two output buffers being delivered as a pair of differential output signals of said operational amplifier.

29. A differential circuit comprising a first differential non-inverting amplifier circuit provided as an initial stage and a second differential non-inverting amplifier circuit provided as stages from a second stage onward;

said first differential non-inverting amplifier circuit including an operational amplifier having a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal serving as a first signal input terminal, second signal input terminal, first signal output terminal and second signal output terminal, respectively;

a first passive element connected between the inverting feedback input terminal and ground;

a second passive element having an impedance equal to that of the first passive element connected between the non-inverting feedback input terminal and ground;

a third passive element connected between the inverting feedback input terminal and the non-inverting output terminal;

a fourth passive element having an impedance equal to that of the third passive element connected between the non-inverting feedback input terminal and the inverting output terminal; and

two balance input terminals;

wherein a constant-voltage level is input to one of said two balance input terminals and a variable voltage level is input to the other of said two balance input terminals;

said second differential non-inverting amplifier circuit including an operational amplifier having a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal serving as a first signal input terminal, second signal input terminal, first signal output terminal and second signal output terminal, respectively;

a first passive element connected between the inverting feedback input terminal and ground;

a second passive element having an impedance equal to that of the first passive element connected between the non-inverting feedback input terminal and ground;

a third passive element connected between the inverting feedback input terminal and the non-inverting output terminal;

a fourth passive element having an impedance equal to that of the third passive element connected between the non-inverting feedback input terminal and the inverting output terminal; and

one balance input terminal;

wherein a constant-voltage level is input to said one balance input terminal.