Push-pull wideband semiconductor amplifier

• US 6,011,438 A
• Filed: 11/19/1998
• Issued: 01/04/2000
• Est. Priority Date: 11/27/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Taguchi, Yuichi, Kakuta, Yuji, Fukasawa, Yoshiaki
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHANH V
• Application Number:
  US09/195,408
• Time in Patent Office: 411 Days
• Field of Search: 330/262, 330/271, 330/272, 330/276, 330/311
• US Class Current: 330/262
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2200/534 Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/63 the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 3/26 Push-pull amplifiers; Phase-splitters therefor duplicated single-ended push-pull arrangements or phase-splitters therefor H03F3/30

Abstract

A push-pull wideband semiconductor amplifier for use in, for example, a CATV (cable television) system. The amplifier suppresses deterioration of composite second-order (CSO) distortion in output signals. The push-pull wideband amplifier includes: a divider which divides a signal inputted by way of an input terminal into two signals of differing phase, first and second amplifying circuits each of which amplifies the signal divided by the divider, and a combiner which combines the two signals amplified by the first and second amplifying circuits into one signal and outputs the result signal. The node between the first amplifying circuit and the second amplifying circuit is an imaginary ground point having a potential of 0 V from the standpoint of an alternating-current signal. A termination circuit is provided between this imaginary ground, point and ground and absorbs fluctuation in potential generated at the imaginary ground point. In the event of fluctuation in potential generated at the imaginary ground point, the fluctuation in potential is absorbed by the termination circuit. The standing wave that accompanies fluctuation in potential is therefore not generated, and even-order distortion is suppressed.

Claims

1. A semiconductor circuit comprising:

a divider which divides an input signal into two signals of differing phase;

first and second amplifying circuits which respectively amplify the signals divided by said divider;

a combiner which combines the two signals amplified by said first and second amplifying circuits and outputs a result signal;

an imaginary ground point which is a node between said first amplifying circuit and said second amplifying circuit having an AC potential essentially of 0 V; and

a termination circuit provided between said imaginary ground point and ground that absorbs fluctuation in said AC potential generated at said imaginary ground point.

2. A semiconductor circuit according to claim 1, wherein said semiconductor circuit is a push-pull amplifying circuit, and wherein the two signals of differing phase have a mutual phase difference of 180 degrees, and wherein said divider distributes the two signals to said first amplifying circuit and said second amplifying circuit, respectively.

3. A semiconductor circuit according to claim 1 wherein said termination circuit consists of a resistor and a capacitor connected in series.

4. A semiconductor circuit according to claim 3 wherein resistance of said resistor is greater than or equal to 10 Ω

and less than or equal to 100 Ω

.

5. A semiconductor circuit according to claim 2 wherein said termination circuit consists of a resistor and a capacitor connected in series.

6. A semiconductor circuit according to claim 5 wherein resistance of said resistor is greater than or equal to 10 Ω

and less than or equal to 100 Ω

.

7. A semiconductor circuit according to claim 2 wherein each of said amplifying circuits comprises:

a first transistor operating as an emitter grounding circuit; and

a second transistor operating as a base grounding circuit and amplifying an output of said first transistor, a base of said second transistor connected to said imaginary ground point by way of a base resistance.

8. A semiconductor circuit according to claim 2 wherein each of said amplifying circuits comprises:

a first FET (field effect transistor) operating as a source grounding circuit; and

a second FET operating as a gate grounding circuit and amplifying an output of said first FET, a gate of said second FET connected to said imaginary ground point by way of a gate resistance.

9. A semiconductor circuit according to claim 2 wherein each of said amplifying circuits is provided with a feedback loop, a plurality of resistance elements, and FETs (field effect transistors) connected in multiple stages.

10. A semiconductor circuit according to claim 9 wherein a gate of at least one FET of said FETs connected in multiple stages is connected to said imaginary ground point by way of a gate resistance.

11. A semiconductor circuit according to claim 10, wherein said gate resistance comprises a plurality of thermistors.