Digital signal processor having an on-chip pipelined EEPROM data memory and a on-chip pipelined EEPROM program memory
First Claim
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1. An integrated circuit formed on a semiconductor substrate comprising:
- a CPU core formed on the semiconductor substrate;
a floating gate memory array coupled to the CPU core and being formed on the same semiconductor substrate, the floating gate memory array comprising;
a data memory portion which is accessed using a first pipelined process; and
a program memory portion which is accessed using a second pipelined process which is different from the first pipelined process.
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Abstract
A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1× and 2× architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.
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Citations
20 Claims
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1. An integrated circuit formed on a semiconductor substrate comprising:
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a CPU core formed on the semiconductor substrate; a floating gate memory array coupled to the CPU core and being formed on the same semiconductor substrate, the floating gate memory array comprising; a data memory portion which is accessed using a first pipelined process; and a program memory portion which is accessed using a second pipelined process which is different from the first pipelined process. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification