Digital signal processor having an on-chip pipelined EEPROM data memory and a on-chip pipelined EEPROM program memory

• US 6,011,719 A
• Filed: 02/01/1999
• Issued: 01/04/2000
• Est. Priority Date: 12/26/1996
• Status: Expired due to Term

• Current Assignee: Progressive Semiconductor Solutions LLC (Acacia Research Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Shin, Jin-Uk "Luke", Wang, Karl L.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/241,150
• Time in Patent Office: 337 Days
• Field of Search: 365/185.21, 365/185.11, 365/189.02, 365/230.02, 365/189.04, 365/230.05
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1× and 2× architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Claims

1. An integrated circuit formed on a semiconductor substrate comprising:

a CPU core formed on the semiconductor substrate;

a floating gate memory array coupled to the CPU core and being formed on the same semiconductor substrate, the floating gate memory array comprising;

a data memory portion which is accessed using a first pipelined process; and

a program memory portion which is accessed using a second pipelined process which is different from the first pipelined process.

2. The integrated circuit of claim 1 comprising:

selection circuitry for selecting at least one of a plurality of bit lines within one of either the data memory portion or the program memory portion to create a selected bit line;

precharge circuitry for precharging a plurality of unselected bit lines, not including the selected bit line, to a selected voltage during a time period when the plurality of unselected bit lines are not selected by the selection circuitry.

3. The integrated circuit of claim 1 wherein one of either the first or second pipelined process uses a master circuit and a slave circuit coupled to the master circuit.

4. The integrated circuit of claim 3 wherein the master circuit is processing a first memory access while the slave circuit is processing a second memory access different from the first memory access.

5. The integrated circuit of claim 1 wherein the master circuit has a storage node and a complementary storage node that are both selectively coupled by logic gates to a reference current source.

6. The integrated circuit of claim 1 wherein the data memory portion and the program memory portion are both EEPROM memory arrays.

7. The integrated circuit of claim 1 comprising:

programming circuitry for programming a memory cell within one of either the data memory portion or the program memory portion;

grounding circuitry for grounding a plurality of unselected bit lines not associated with the memory cell during a time period when memory cell is being programmed.

8. The integrated circuit of claim 1 wherein one of either the data memory portion or the program memory portion are providing data at output terminals at a rate of 100 MHz or greater.

9. The integrated circuit of claim 1 wherein one of either the data memory portion or the program memory portion have a first circuit portion serially coupled to a second circuit portion wherein the first circuit portion is performing data output operations for a first memory access while the second circuit is performing address provision for a second memory access different from the first memory access.

10. The integrated circuit of claim 9 wherein the second circuit also performs address decoding and bit line precharging for the second memory access while the first circuit is providing output data for the first memory access.

11. The integrated circuit of claim 9 wherein the second circuit also performs word line selection and data sensing operations for the second memory access while the first circuit is providing output data for the first memory access.

12. The integrated circuit of claim 1 wherein one of either the data memory portion or the program memory portion performs the following pipeline operations in order:

(1) address provision for a memory access;

(2) address decoding and bit line precharge for the memory access;

(3) word line selection for the memory access;

(4) data sensing operations for the memory access; and

(5) data output provision for the memory access.

13. The integrated circuit of claim 1 wherein one of either the data memory portion or the program memory portion has a first circuit portion serially coupled to a second circuit portion wherein the first circuit portion is performing data output operations for a first memory access while the second circuit is performing address decode and bit line precharging for a second memory access different from the first memory access.

14. The integrated circuit of claim 13 wherein the second circuit also performs address latching and word line selection for the second memory access while the first circuit is providing output data for the first memory access.

15. The integrated circuit of claim 14 wherein the second circuit also performs data sensing operations for the second memory access while the first circuit is providing output data for the first memory access.

16. The integrated circuit of claim 1 wherein one of either the data memory portion or the program memory portion performs the following pipeline operations in order:

(1) address provision for a memory access;

(2) address latching and decoding for the memory access;

(3) word line selection and bit line precharging for the memory access;

(4) at least two clock cycles of data sensing operations for the memory access; and

(5) at least two clock cycles of data output provision for the memory access.

17. The integrated circuit of claim 1 wherein one of either the data memory portion or the program memory portion performs the following pipeline operations in order:

(1) at least three clock cycles of address processing for a memory access;

(2) word line latching and bit line precharge for the memory access;

(3) at least three clock cycles of sense and precharge operations for the memory access;

(4) sense latch operations for the memory access; and

(5) at least two clock cycles of data output provision for the memory access.

18. The integrated circuit of claim 1 wherein one of either the data memory portion or the program memory portion has a first circuit portion serially coupled to a second circuit portion wherein the first circuit portion is performing data output operations for a first memory access while the second circuit is performing data sense operations for a second memory access different from the first memory access.

19. The integrated circuit of claim 18 wherein the second circuit also performs address processing for the second memory access while the first circuit is performing sense operations for the first memory access.

20. The integrated circuit of claim 18 wherein the second circuit performs word line latch and bit line precharge operations for a second memory access while the first circuit is providing output data and performing data sense operations for the first memory access.