Nonvolatile memory with reduced write time/write verify time and semiconductor device thereof

• US 6,011,720 A
• Filed: 06/03/1998
• Issued: 01/04/2000
• Est. Priority Date: 01/13/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tanaka, Nobuhiko
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/089,765
• Time in Patent Office: 580 Days
• Field of Search: 365/185.22, 365/185.11, 365/185.12, 365/185.13, 365/185.23
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

An involatile memory which carries out, in a flash memory itself, verify check of the flash memory for respective bit lines, and produces an overall verify check result from a completion decision circuit to a tester. This makes it possible to solve a problem of a conventional flash memory in that the time taken by the verify check depends on the bus width of an external data bus, because it carries out the verify check by reading data from the flash memory through the external bus. Thus, the time taken by the verify check can be reduced.

Claims

1. An involatile memory comprising:

P memory cell sub-arrays, each of which includes M×

N memory transistors, where P, M and N are each an integer equal to or greater than one;

P sets of bit lines, each of said P sets including M bit lines each of which is directly connected to N memory transistors of said M×

N memory transistors;

P decoders, each of which is connected to the M bit lines of one of said P sets of bit lines, for selecting one of said M bit lines in response to an address signal;

P I/O drivers, each of which connects the bit line selected by each of said P decoders to an external bus line;

sense amplifiers, coupled between said memory cell sub-arrays and said decoders, for detecting outputs of said memory transistors, and for generating logic level signals in response to said outputs;

verify check circuits, connected to outputs of said sense amplifiers, respectively, for detecting levels of data in said memory transistors in response to the outputs of said sense amplifiers; and

a completion decision circuit that receives check results of said verify check circuits, and produces a verify completion signal when the entire received check results are correct.

2. The involatile memory as claimed in claim 1, wherein each of said P decoders comprises:

a plurality of first decoders, each of which is connected to multiple bit lines of said M bit lines, for selecting one of said multiple bit lines in response to the address signal; and

a second decoder for selecting one of outputs of said plurality of first decoders in response to the address signal,

wherein said sense amplifiers are connected between said plurality of first decoders and said second decoder.

3. The involatile memory as claimed in claim 1, wherein said completion decision circuit comprises a plurality of completion decision sub-circuits, each of which are provided for every 8 bits or 16 bits of I/O ports of said P I/O drivers.

4. A semiconductor device comprising:

P memory cell sub-arrays, each of which includes M×

N memory transistors, where P, M and N are each an integer equal to or greater than one;

P sets of bit lines, each of said P sets including M bit lines each of which is directly connected to N memory transistors of said M×

N memory transistors;

P decoders, each of which is connected to the M bit lines of one of said P sets of bit lines, for selecting one of said M bit lines in response to an address signal;

P I/O drivers, each of which connects the bit line selected by each of said P decoders to an internal bus line in said semiconductor device;

sense amplifiers, coupled between said memory cell sub-arrays and said decoders, for detecting outputs of said memory transistors, and for generating logic level signals in response to said outputs;

verify check circuits, connected to outputs of said sense amplifiers, respectively, for detecting levels of data in said memory transistors in response to the outputs of said sense amplifiers; and

a completion decision circuit that receives check results of said verify check circuits, and produces a verify completion signal when the entire received check results are correct.

5. The semiconductor device as claimed in claim 4, wherein each of said P decoders comprises:

a plurality of first decoders, each of which is connected to multiple bit lines of said M bit lines, for selecting one of said multiple bit lines in response to the address signal; and

a second decoder for selecting one of outputs of said plurality of first decoders in response to the address signal,

wherein said sense amplifiers are connected between said plurality of first decoders and said second decoder.

6. The semiconductor device as claimed in claim 4, wherein said completion decision circuit comprises a plurality of completion decision sub-circuits, each of which are provided for every 8 bits or 16 bits of I/O ports of said P I/O drivers.