Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

• US 6,011,725 A
• Filed: 02/04/1999
• Issued: 01/04/2000
• Est. Priority Date: 08/01/1997
• Status: Expired due to Term

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thong
• Application Number:
  US09/246,183
• Time in Patent Office: 334 Days
• Field of Search: 365/185.33, 365/185.14, 365/185.29, 365/131
• US Class Current: 365/185.33
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively.

Claims

1. A method of programming, reading, and erasing an electrically erasable programmable read only memory (EEPROM) cell capable of storing two binary information bits, said memory cell having a first region and a second region with a channel therebetween and having a gate above said channel but separated therefrom by a non conductive charge trapping material sandwiched between first and second silicon dioxide layers, said method comprising:

programming a first bit in a first forward direction to represent a first binary value by applying programming voltages to said first region and to said gate and grounding said second region, thereby injecting and storing electrical charge in a first charge trapping region of said charge trapping material positioned asymmetrically close to said first region, or to represent a second binary value by not injecting electrical charge into said first charge trapping region;

programming a second bit in a second forward direction opposite said first forward direction to represent a third binary value by applying programming voltages to said second region and to said gate and grounding said first region, thereby injecting and storing electrical charge in a second charge trapping region of said charge trapping material positioned asymmetrically close to said second region, or to represent a fourth binary value by not injecting electrical charge into said second charge trapping region;

reading said first bit in a direction opposite said first forward direction by applying read voltages to said second region and said gate and grounding said first region, and subsequently determining if said first binary value is stored by sensing a first current between said second and said first regions or if said second binary value is stored by sensing a second current between said second and said first regions, said second current being higher than said first current;

reading said second bit in a direction opposite said second forward direction by applying read voltages to said first region and said gate and grounding said second region, and subsequently determining if said third binary value is stored by sensing a third current between said first and said second regions or if said fourth binary value is stored by sensing a fourth current between said first and said second regions, said fourth current being higher than said third current;

erasing said first bit by applying erasing voltages to said gate and said first region so as to cause electrical charge representing said first binary value to be removed from said first charge trapping region; and

erasing said second bit by applying erasing voltages to said gate and said second region so as to cause electrical charge representing said second binary value to be removed from said second charge trapping region.

2. The method according to claim 1, wherein the gate voltage during said reading said first bit or said second bit is a voltage generating sufficient inversion in said channel to allow sensing a binary value represented by no trapped charge of the bit to be read, and permitting read through of the bit not being read.

12. The method according to claim 1 wherein said first current is approximately zero and said third current is approximately zero.

13. The method according to claim 1 wherein said electrical charge in said first charge trapping region comprises electrons and said electrical charge in said second charge trapping region comprises electrons.

3. A method of programming, reading, and erasing an electrically erasable programmable read only memory (EEPROM) cell capable of storing two binary information bits, said memory cell having a first region, a second region spaced from said first region, a channel between said first region and said second region, a gate, and a non conductive charge trapping material sandwiched between first and second silicon dioxide layers formed between said gate and said channel, said method comprising:

programming a first bit in a first forward direction to represent a first binary value by applying programming voltages to said first region and to said gate and a reference voltage to said second region, thereby injecting electrical charge into a first charge trapping region of said charge trapping material positioned asymmetrically close to said first region, or to represent a second binary value by not injecting electrical charge into said first charge trapping region;

programming a second bit in a second forward direction opposite said first forward direction to represent a third binary value by applying programming voltages to said second region and to said gate and said reference voltage to said first region, thereby injecting electrical charge into a second charge trapping region of said charge trapping material positioned asymmetrically close to said second region, or to represent a fourth binary value by not injecting electrical charge into said second charge trapping region;

reading said first bit in a direction opposite said first forward direction by applying read voltages to said second region and said gate and said reference voltage to said first region, and subsequently determining if said first binary value is stored by sensing a first current between said second and said first regions or if said second binary value is stored by sensing a second current between said second and said first regions, said second current being higher than said first current;

reading said second bit in a direction opposite said second forward direction by applying read voltages to said first region and said gate and applying said reference voltage to said second region, and subsequently determining if said third binary value is stored by sensing a third current between said second and said first regions or if said fourth binary value is stored by sensing a fourth current between said second and said first regions, said fourth current being higher than said third current;

erasing said first bit by applying a selected potential to said gate so as to cause said electrical charge, if any, in said first charge trapping region to be removed from said first charge trapping region via said first region; and

erasing said second bit by applying a selected potential to said gate so as to cause said electrical charge, if any, in said second charge trapping region to be removed from said second charge trapping region via said second region.

4. The method according to claim 3, wherein the selected potential applied to said gate is ground potential.

5. The method according to claim 3, wherein the selected potential applied to said gate is a negative potential.

14. The method according to claim 3 wherein said electrical charge, if any, in said first charge trapping region comprises electrons and said electrical charge, if any, in said second charge trapping region comprises electrons.

15. The method according to claim 3 wherein said reference voltage is ground.

6. A method of programming, reading, and erasing an electrically erasable programmable read only memory (EEPROM) cell capable of storing two bits of information, said memory cell having a semiconducting substrate of a first conductivity type, a first region of a second conductivity type opposite to said first conductivity type, a second region of said second conductivity type, said second region being spaced from said first region, a channel formed in said substrate between said first region and said second region, a conductive gate, and a non conductive charge trapping material sandwiched between first and second silicon dioxide layers formed between said gate and said channel, said method comprising:

(a) programming a first bit to represent a first binary value by;

applying a first programming voltage to said gate;

applying a second programming voltage to said first region; and

coupling said second region to ground;

thereby to inject electrical charge into said charge trapping material utilizing hot electron injection for a time sufficient to cause enough electrons to become trapped in a first charge trapping region positioned asymmetrically in said charge trapping material in close vicinity to said first region such that a threshold voltage of said cell is at least at a predetermined level when said cell is read in a direction opposite the direction used during said programming to represent said first binary value;

or

programming said first bit to represent a second binary value by not injecting electrical charge into said first charge trapping region;

(b) programming a second bit to represent a third binary value by;

applying a third programming voltage to said gate;

applying a fourth programming voltage to said second region; and

coupling said first region to ground;

thereby to inject electrical charge into said charge trapping material utilizing hot electron injection for a time sufficient to cause enough electrons to become trapped in a second charge trapping region positioned asymmetrically in said charge trapping material in close vicinity to said second region such that a threshold voltage of said cell is at least at a predetermined level when said cell is read in a direction opposite the direction used during said programming to represent said second binary value;

or

programming said second bit to represent a second binary value by not injecting electrical charge into said second charge trapping region;

(c) reading said first bit by;

applying a first read voltage to said gate;

applying a second read voltage to said second region;

coupling said first region to ground; and

sensing a current level between said second region and said first region;

wherein said first read voltage is sufficient to generate inversion in said channel that allows sensing said second binary value regardless of the programmed state of said second bit;

(d) reading said second bit by;

applying a third read voltage to said gate;

applying a fourth read voltage to said first region;

coupling said second region to ground; and

sensing a current level between said first region and said second region;

wherein said third read voltage is sufficient to generate inversion in said channel that allows sensing said fourth binary value regardless of the programmed state of said first bit;

(e) erasing said first bit by;

applying a first erase voltage to said gate; and

applying a second erase voltage to said first region;

wherein said first and second erase voltages are sufficient to cause electrons to be removed from said first charge trapping region; and

(f) erasing said second bit by;

applying a third erase voltage to said gate; and

applying a fourth erase voltage to said second region;

wherein said third and fourth erase voltages are sufficient to cause electrons to be removed from said second charge trapping region.

7. A method of operating a non-volatile electrically erasable and programmable semiconductor memory cell capable of storing two bits of information by using asymmetrical charge trapping, said memory cell comprising a semiconductor substrate of a first conductivity type having formed therein a first region and a second region each of a second conductivity type opposite said first conductivity type, said memory cell further having formed therein a channel between said first and second regions, a dielectric overlying said channel, said dielectric including at least a silicon nitride layer formed for the capture and retention of localized charge in a first trapping portion of said silicon nitride layer close to said first region and in a second trapping portion of said silicon nitride layer close to said second region, and a conductive gate overlying said dielectric, said method comprising:

representing a first binary value in a first information bit by placing electrical charge in said first trapping portion or representing a second binary value in said first information bit by not placing electrical charge in said first trapping portion;

representing a third binary value in a second information bit by placing electrical charge in said second trapping portion or representing a fourth binary value in said second information bit by not placing electrical charge in said second trapping portion;

applying a first voltage to said second region greater than a voltage on said first region and applying a second voltage to said gate, said second voltage causing a first current between said first and said second regions when no charge has been placed in said first trapping portion and causing a second current, less than said first current, or no current, between said first and said second regions when a first localized charge has been placed in said first trapping portion, said first localized charge being substantially less than a localized charge required to achieve the same threshold voltage for said cell when said cell is to be read by applying a voltage to said first region greater than a voltage on said second region, and a voltage to said gate; and

applying a third voltage to said first region greater than a voltage on said second region and applying a fourth voltage to said gate, said fourth voltage causing a third current between said first and said second regions when no charge has been placed in said second trapping portion and causing a fourth current, less than said third current, or no current, between said first and said second regions when a second localized charge has been placed in said second trapping portion, said second localized charge being substantially less than a localized charge required to achieve the same threshold voltage for said cell when said cell is read by applying a voltage to said second region greater than a voltage on said first region, and a voltage to said gate.

16. The method according to claim 7 wherein said electrical charge in said first trapping portion representing said first binary value comprises electrons, and said electrical charge in said second trapping portion representing said third binary value comprises electrons.

8. A method of storing and using two bits of information in a memory cell, the memory cell comprising a semiconductor substrate of a first conductivity type with a first region of a second conductivity type opposite to said first conductivity type and a second region of second conductivity type opposite to said first conductivity type formed therein, a channel in said substrate separating said first region from said second region, a multi-layer dielectric formed over said channel and having a first end adjacent said first region and a second end adjacent said second region, and a conductive gate formed over said multi-layer dielectric, said method comprising:

(a) programming the binary state of a first information bit by placing a first selected charge within said first end of said dielectric when representing a first binary value or placing less than said first selected charge within said first end of said dielectric when representing a second binary value; and

(b) programming the binary state of a second information bit by placing a second selected charge within said second end of said dielectric when representing a third binary value or placing less than said second selected charge within said second end of said dielectric when representing a fourth binary value;

(c) reading the state of said first information bit by;

applying a first selected voltage to said second region;

applying a second selected voltage to said conductive gate; and

applying a ground potential to said first region;

wherein a current above a first threshold current flows in said channel when said first selected charge is below a selected amount and no current or a current beneath said first threshold current flows in said channel when said first selected charge is above said selected amount; and

(d) reading the state of said second information bit by;

applying said first selected voltage to said first region;

applying said second selected voltage to said conductive gate; and

applying a ground potential to said second region;

wherein a current above a second threshold current flows in said channel when said second selected charge is below said selected amount and no current or a current beneath said second threshold current flows in said channel when said second selected charge is above said selected amount.

9. The method of claim 8:

wherein said first information bit is erased by applying a first positive voltage to said first region and applying a voltage less than said first positive voltage to said conductive gate, thereby to remove said first selected charge from said dielectric; and

wherein said second information bit is erased by applying a second positive voltage to said second region and applying a voltage less than said second positive voltage to said conductive gate, thereby to remove said second selected charge from said dielectric.

10. A method enabling a two bit storage device comprising:

(a) providing a device comprising;

a semiconductor substrate of a first conductivity type;

a first region and a second region, each of a second conductivity type opposite said first conductivity type, each formed in said substrate and separated from each other by a channel region;

a multi-layer dielectric, formed over said channel region, having a first end adjacent said first region and a second end adjacent said second region; and

a conductive gate formed over said multi-layer dielectric and adapted to control current in said channel between said first and said second regions;

(b) representing a first binary value in a first bit by placing a first amount of charge in said first end of said multi-layer dielectric or representing a second binary value in said first bit by not placing a charge in said first end of said multi-layer dielectric;

(c) representing a third binary value in a second bit by placing a second amount of charge in said second end of said multi-layer dielectric or representing a fourth binary value in said second bit by not placing a charge in said second end of said multi-layer dielectric;

(d) reading the binary state of said first bit by applying a first voltage to said first region, a second voltage to said second region, and a third voltage to said gate, wherein said first, said second, and said third voltages are selected to allow a first current in said channel region between said first and said second regions when said second binary value is represented, regardless of the binary state of said second bit, but not to allow said first current when said first binary value is represented; and

(e) reading the binary state of said second bit by applying a fourth voltage to said first region, a fifth voltage to said second region, and a sixth voltage to said gate, wherein said fourth, said fifth, and said sixth voltages are selected to allow a second current in said channel region between said second and said first regions when said fourth binary value is represented, regardless of the binary state of said first bit, but not to allow said second current when said third binary value is represented.

11. The method of claim 10 comprising:

(f) erasing the binary state of said first bit by removing charge from said first end of said multi-layer dielectric; and

(g) erasing the binary state of said second bit by removing charge from said second end of said multi-layer dielectric.