Device and method for testing a circuit

• US 6,011,736 A
• Filed: 02/25/1999
• Issued: 01/04/2000
• Est. Priority Date: 05/13/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beigel, Kurt D., Cutter, Douglas J.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/258,096
• Time in Patent Office: 313 Days
• Field of Search: 365/201, 365/205, 365/207, 365/208, 365/203, 365/200
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp'"'"'s voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp'"'"'s ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

Claims

1. A method for testing a semiconductor memory device having at least one sense amp, comprising:

writing original data to said memory device;

driving said sense amp with a first voltage;

reading a first sample of stored data from said memory device;

driving said sense amp with a different voltage;

reading an additional sample of stored data from said memory device; and

comparing said first sample of stored data and said additional sample of stored data with said original data.

2. A method for determining the range of margins that a voltage-pulling sense amp transistor of a memory array is capable of accommodating, comprising:

entering an input test pattern into said memory array;

reading at least two output test patterns using at least two voltage levels driving said voltage-pulling sense amp transistor; and

comparing said input test pattern with said output test patterns.

3. A method for determining a lowest reliable level of a supply voltage capable of driving a sense amp in a memory array, comprising:

writing initial test data to said memory array;

initiating a test mode;

taking a plurality of test readings from said memory array;

decreasing said supply voltage driving said sense amp for each of said plurality of test readings; and

repeating taking test readings and decreasing said supply voltage.

4. The method in claim 3, wherein said repeating further comprises repeating taking test readings and decreasing said supply voltage until current saturation occurs.

5. The method in claim 4, wherein initiating a test mode comprises providing electrical communication between a test pathway and said sense amp.

6. The method in claim 5, wherein initiating a test mode further comprises preventing electrical communication between a non-test operation pathway and said sense amp.

7. The method in claim 6, wherein decreasing said supply voltage comprises decreasing said supply voltage-through a range of voltages.

8. A method for determining a highest reliable level of a supply voltage that can drive a sense amp in a memory array, comprising:

writing initial test data to said memory array;

taking a plurality of test readings from said memory array;

increasing said supply voltage driving said sense amp for each of said plurality of test readings; and

repeating taking test readings and increasing said supply voltage until capacitive coupling occurs.

9. The method in claim 8, wherein increasing said supply voltage comprises increasing said supply voltage through a series of discrete values.

10. A method of test driving a sense amp voltage puller for at least one memory cell, comprising:

entering an input value to said memory cell;

providing a plurality of driving pathways to said sense amp voltage puller;

configuring each driving pathway of said plurality of driving pathways to accept at least a respective plurality of voltage sources;

associating said plurality of driving pathways with a plurality of test vectors;

transmitting a test vector corresponding to one driving pathway of said plurality of driving pathways;

enabling electrical communication between said sense amp voltage puller and said driving pathway corresponding to said test vector;

reading a first sample of output data;

transmitting a different test vector corresponding to a different driving pathway;

enabling electrical communication between said sense amp voltage puller and said different driving pathway; and

reading a second sample of output data.

11. The method in claim 10, wherein enabling electrical communication comprises enabling electrical communication through one of said driving pathways at a time.

12. A method of determining the margin that a voltage-pulling transistor of a memory array is capable of accommodating, comprising:

entering an input data pattern to said memory array;

repeatedly reading an output data pattern from said memory array;

changing a voltage level driving said voltage-pulling transistor for each reading; and

tracking any differences between said output data pattern and said input data pattern.

13. A method for determining operable drive levels for a pulldown sense amp accommodating an operations circuit, wherein said pulldown sense amp has a first portion at a first voltage level and a second portion at a second voltage level, comprising:

setting an initial drive level for said pulldown sense amp;

pulling down said first voltage level for a first time;

establishing a new drive level for said pulldown sense amp;

pulling down said first voltage level for a second time; and

selectively comparing one time span required to pull down said first voltage level with a time span for accessing one of said first and second portions by said operations circuit.

14. The method in claim 13, further comprising equilibrating said first voltage level and said second voltage level before each pulling.

15. A method for determining the capabilities of a pullup transistor serving external circuitry, wherein said pullup transistor is coupled to at least one sense amp, comprising:

initiating a test drive voltage for said pullup transistor;

pulling up a digit-line voltage of a component of said sense amp associated with said pullup transistor;

comparing a length of time needed to pull up said digit-line voltage with a length of time required to drive said external circuitry;

altering said test drive voltage; and

repeating said pulling and comparing.

16. The method in claim 15, further comprising altering said test drive voltage before every repetition of said pulling.

17. The method in claim 16 further comprising establishing a non-test drive voltage within a range capable of pulling up said digit-line voltage within said length of time required to drive said external circuitry.

18. The method in claim 17, wherein said non-test drive voltage is generally constant.