Shared pull-up and selection circuitry for programmable cells such as antifuse cells

• US 6,011,742 A
• Filed: 08/20/1997
• Issued: 01/04/2000
• Est. Priority Date: 08/01/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zheng, Hua
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US08/915,312
• Time in Patent Office: 867 Days
• Field of Search: 365/225.7, 365/200, 365/100, 365/96
• US Class Current: 365/225.7
• CPC Class Codes: G11C 29/781 combined in a redundant decoder
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V_CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry. A transistor having a large channel resistance, however, is placed within a feedback path of the latch. Therefore, after the latch is set, if the antifuse cell is blown, the high resistance transistor provides a resistive current path from the V_CC to ground.

Claims

1. A semiconductor memory device coupled to first and second voltage supply terminals, comprising:

a plurality of rows and columns of primary and redundant memory cells;

a plurality of electronically programmable resistance circuits, each storing at least one bit of information of an address of one of the plurality of rows of primary memory cells, and at least one bit of information of an address of one of the plurality of columns of primary memory cells, each programmable resistance circuit comprising;

first and second programmable resistance cells each coupled to the first voltage supply terminal;

a single shared selection circuit coupled to both of the first and second programmable resistance cells and having an output terminal, the single shared selection circuit selectively providing first and second bits of information from the first and second programmable resistance cells to the output terminal upon receipt of first and second selection signals supplied thereto, respectively;

a single output circuit coupled to the second voltage supply terminal and the output terminal of the single shared selection circuit and having a data output terminal, the output circuit providing the first and second bits of information for the first and second programmable resistance cells to the data output terminal, and

wherein the first and second programmable resistance cells are antifuse cells, wherein the first and second voltage supply terminals provide ground and positive voltage, respectively, wherein the shared selection circuit includes first and second selection transistors, the first selection transistor being coupled between a second terminal of the first antifuse cell and the output terminal, and receiving the first selection signal at a control terminal, and the second selection transistor being coupled between a second terminal of the second antifuse cell and the output terminal, and receiving the second selection signal at a control terminal; and

wherein the output circuit includes an inverter, a resistive element, and first and second latch transistors, the first and second latch transistors having first terminals coupled to receive the positive voltage, the resistive element being coupled between a second terminal of the first latch transistor and the output terminal of the shared selection circuit, the inverter being coupled between the output terminal and the data output terminal, a second terminal of the second latch transistor being coupled to the second terminal of the first latch transistor, a control terminal of the first latch transistor receiving an enabling signal, and a control terminal of the second latch transistor being coupled to the data output terminal.

2. A semiconductor memory device coupled to first and second voltage supply terminals, comprising:

a plurality of rows and columns of primary and redundant memory cells;

a plurality of electronically programmable resistance circuits, each storing at least one bit of information of an address of one of the plurality of rows of primary memory cells, and at least one bit of information of an address of one of the plurality of columns of primary memory cells, each programmable resistance circuit comprising;

first and second programmable resistance cells each coupled to the first voltage supply terminal;

a single shared selection circuit coupled to both of the first and second programmable resistance cells and having an output terminal, the single shared selection circuit selectively providing first and second bits of information from the first and second programmable resistance cells to the output terminal upon receipt of first and second selection signals supplied thereto, respectively;

a single output circuit coupled to the second voltage supply terminal and the output terminal of the single shared selection circuit and having a data output terminal, the output circuit providing the first and second bits of information for the first and second programmable resistance cells to the data output terminal, and

wherein the first and second programmable resistance cells are antifuse cells, wherein the shared selection circuit includes first and second switch elements, the first switch element being coupled between a second terminal of the first antifuse cell and the output terminal, and receiving the first selection signal at a control terminal, and the second switch element being coupled between a second terminal of the second antifuse cell and the output terminal, and receiving the second selection signal at a control terminal.

3. A semiconductor memory device coupled to first and second voltage supply terminals, comprising:

a plurality of rows and columns of primary and redundant memory cells;

a plurality of electronically programmable resistance circuits, each storing at least one bit of information of an address of one of the plurality of rows of primary memory cells, and at least one bit of information of an address of one of the plurality of columns of primary memory cells, each programmable resistance circuit comprising;

first and second programmable resistance cells each coupled to the first voltage supply terminal;

a single shared selection circuit coupled to both of the first and second programmable resistance cells and having an output terminal, the single shared selection circuit selectively providing first and second bits of information from the first and second programmable resistance cells to the output terminal upon receipt of first and second selection signals supplied thereto, respectively;

a single output circuit coupled to the second voltage supply terminal and the output terminal of the single shared selection circuit and having a data output terminal, the output circuit providing the first and second bits of information for the first and second programmable resistance cells to the data output terminal, and

wherein the first and second programmable resistance cells are antifuse cells, wherein the first and second voltage supply terminals provide ground and positive voltage, respectively, and wherein the output circuit includes a pull-up circuit coupled between the output terminal of the selection circuit to provide a high voltage value to the data output terminal if the first or second antifuse cell remains intact.

4. A semiconductor memory device coupled to first and second voltage supply terminals, comprising:

a plurality of rows and columns of primary and redundant memory cells;

a plurality of electronically programmable resistance circuits, each storing at least one bit of information of an address of one of the plurality of rows of primary memory cells, and at least one bit of information of an address of one of the plurality of columns of primary memory cells, each programmable resistance circuit comprising;

first and second programmable resistance cells each coupled to the first voltage supply terminal;

a single shared selection circuit coupled to both of the first and second programmable resistance cells and having an output terminal, the single shared selection circuit selectively providing first and second bits of information from the first and second programmable resistance cells to the output terminal upon receipt of first and second selection signals supplied thereto, respectively;

a single output circuit coupled to the second voltage supply terminal and the output terminal of the single shared selection circuit and having a data output terminal, the output circuit providing the first and second bits of information for the first and second programmable resistance cells to the data output terminal, and

wherein the output circuit includes a latch circuit coupled between the output terminal of the selection circuit and the data output terminal to latch the first or second bits of information to the data output terminal in response to the first or second selection signals applied to the selection circuit, respectively.

5. A semiconductor memory device coupled to first and second voltage supply terminals, comprising:

a plurality of rows and columns of primary and redundant memory cells;

a plurality of electronically programmable resistance circuits, each storing at least one bit of information of an address of one of the plurality of rows of primary memory cells, and at least one bit of information of an address of one of the plurality of columns of primary memory cells, each programmable resistance circuit comprising;

first and second programmable resistance cells each coupled to the first voltage supply terminal;

a single shared selection circuit coupled to both of the first and second programmable resistance cells and having an output terminal, the single shared selection circuit selectively providing first and second bits of information from the first and second programmable resistance cells to the output terminal upon receipt of first and second selection signals supplied thereto, respectively;

a single output circuit coupled to the second voltage supply terminal and the output terminal of the single shared selection circuit and having a data output terminal, the output circuit providing the first and second bits of information for the first and second programmable resistance cells to the data output terminal, and

wherein the first and second voltage supply terminals provide ground and positive voltage, respectively, wherein the output circuit includes a pull-up and latch circuit having an inverter, first and second resistive elements, and first and second latch transistors, the first and second latch transistors having first terminals coupled to receive the positive voltage supply, the first resistive element having first and second resistive element terminals coupled between the second terminal of the first latch transistor and the output terminal of the selection circuit, respectively, the second resistive element having first and second resistive element terminals coupled between the second terminals of the first and second latch transistors, the inverter being coupled between the output terminal and the data output terminal, a control terminal of the first latch transistor receiving a pulsed enabling signal, a control terminal of the second latch transistor being coupled to the data output terminal, and

wherein the first resistive element is a transistor having a control terminal coupled to one of the first and second voltage supply terminals, and has a low channel resistance between the first and second resistive element terminals, and wherein the second resistive element is a transistor having a control terminal coupled to one of the first and second voltage supply terminals, and having a high channel resistance between the first and second resistive element terminals.

6. A comparison circuit for generating a signal corresponding to the address of a defective row or column when a row or column of a memory array is being addressed, the address of the defective row or column being programmed into the comparison circuit, the comparison circuit comprising:

a plurality of programmable row resistance elements having a programmed resistance of one value and an unprogrammed resistance of another value, the row resistance elements corresponding to respective bits of the address of the defective row, each of the row resistance elements having either the unprogrammed resistance value or the programmed resistance value as a function of a programming signal applied to each of the row resistance elements;

a plurality of programmable column resistance elements having a programmed resistance of one value and an unprogrammed resistance of another value, the column resistance elements corresponding to respective bits of the address of the defective column, each of the column resistance elements having either the unprogrammed resistance value or the programmed resistance value as a function of a programming signal applied to each of the column resistance elements, each of the column resistance elements being paired with a row resistance element;

a programming circuit for each of the pairs of row and column resistance elements, the programming circuit selectively generating the programming signal at a programming output;

a sense circuit for each of the pairs of row and column resistance elements, the sense circuit generating a match signal at an output when a sense input to the sense circuit is connected to a resistance having the programmed resistance value; and

a switching circuit for each of the pairs of row and column resistance elements, the switching circuit selectively connecting the programming output of the programming circuit to its corresponding row resistance element when the row resistance elements are to be programmed with the address of a defective row, selectively connecting the programming output of the programming circuit to its corresponding column resistance element when the column resistance elements are to be programmed with the address of a defective row, selectively connecting the input of the sense circuit to its corresponding row resistance element when a row of the memory array is being addressed, and selectively connecting the input of the sense circuit to its corresponding column resistance element when a column of the memory array is being addressed whereby the match signals from all of the sense circuits correspond to the address of a defective row when a row of the memory array is being addressed and to the address of a defective column when a column of the memory array is being addressed.

7. A read circuit for reading the resistance of a programmable resistance element having either a programmed resistance value or an unprogrammed resistance value, the method comprising:

a relatively low current source capable of generating only a relatively low current at an output, the output of the relatively low current source being coupled to the programmable resistance element responsive to a first control signal;

a relatively high current source capable of generating a relatively high current at an output, the output of the relatively high current source being coupled to the programmable resistance element responsive to a second control signal;

a control circuit generating the first control signal during a read period when the resistance of the programmable resistance element is to be determined, the control circuit generating the second control signal during the initial portion of the read period for a duration that is substantially shorter than the read period; and

a voltage sensing circuit having an input coupled to the programmable resistance element, the voltage sensing circuit determining the voltage across the programmable resistance element and generating at an output a sense signal indicative of the resistance of the programmable resistance element.