Received signal strength detecting circuit

• US 6,011,963 A
• Filed: 07/29/1997
• Issued: 01/04/2000
• Est. Priority Date: 08/01/1996
• Status: Expired due to Term

• Current Assignee: Lenovo Innovations Ltd Hong Kong (Lenovo Group Ltd.)
• Original Assignee: NEC Corporation
• Inventors: Ogoro, Kazuo
• Primary Examiner(s): LE, THANH C
• Application Number:
  US08/902,279
• Time in Patent Office: 889 Days
• Field of Search: 455/200.1, 455/226.1, 455/226.2, 455/226.3, 455/226.4, 455/250.1, 455/303, 455/304, 455/315, 455/245.1, 455/254.1
• US Class Current: 455/226.2
• CPC Class Codes: H04B 17/318 Received signal strength

Abstract

A received input signal 10 is received by a reception circuit 20 and a modulator 21, and demodulated data 12 and a reception level signal 16 are obtained. A modulator 23 reconstitutes a modulated wave 13 from the demodulated data 12, and an amplitude detector 21 detects the amplitude of the modulated wave, thus taking out amplitude level variations of the received wave due to modulation components. An analog subtractor 27 cancels the amplitude level variation component with respect to the reception level signal of the received wave. With the cancellation of the amplitude level variations of the received wave due to modulation components, it is possible to follow up quick amplitude level variation of the received wave.

Claims

1. A received signal strength detecting circuit for outputting a reception level signal in which a received modulation signal is demodulated, the demodulated signal is modulated, and the amplitude data of the modulated signal is subtracted from the received signal.

2. The received signal strength detecting circuit according to claim 1, the amplitude data of the modulated signal is logarithmically converted to produce the data to be subtracted.

3. The received signal strength detecting circuit according to claim 1, the received signal is delayed for a predetermined time and outputted as the received signal.

4. The received signal strength detecting circuit according to claim 1, wherein waveform of the modulated wave is produced from the demodulated data.

5. The received signal strength detecting circuit according to claim 1, wherein waveform of the modulated wave is preliminarily stored in a ROM and read out on the basis of the demodulated data.

6. A received signal strength detecting circuit comprising:

a demodulator for demodulating a received signal;

a modulator for reconstituting a modulated wave by modulating the demodulated data;

an amplitude detector for detecting the amplitude of the modulated wave and providing an amplitude signal;

a logarithmic converter for converting the amplitude signal to match the scale thereof to the scale of the received signal;

a delay circuit for delaying the received signal for a predetermined time; and

a subtractor for taking the difference between the amplitude signal and the delayed received signal.

7. A received signal strength detecting circuit comprising:

a demodulator for demodulating a received signal;

a modulator for reconstituting a modulated wave by modulating the demodulated data;

a waveform means for outputting a digital waveform signal of the modulated wave;

D/A converter for converting the digital waveform into an analog signal;

a low pass filter for attenuating unnecessary harmonic components of the output of the D/A converter;

an amplitude detector for detecting the amplitude of the output of the low pass filter signal;

a logarithmic converter for converting the amplitude signal to match the scale thereof to the scale of the received signal;

a delay circuit for delaying the received signal for a predetermined time; and

a subtractor for taking the difference between the amplitude signal and the delayed received signal.

8. The received signal strength detecting circuit according to claim 7, wherein the waveform means is ROM.