Microcontroller having a page address mode

• US 6,012,128 A
• Filed: 10/14/1997
• Issued: 01/04/2000
• Est. Priority Date: 09/16/1994
• Status: Expired due to Fees

• Current Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Birns, Neil E., Mizrahi-Shalom, Ori K.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US08/999,667
• Time in Patent Office: 812 Days
• Field of Search: 711/5, 711/100, 711/154, 711/152, 711/145, 711/163, 711/2, 711/157, 713/1
• US Class Current: 711/163
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 9/342 Extension of operand address space
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A microcontroller with a page zero mode where a memory address space is restricted to one page of a multiple page address space to produce improved performance. Address mapping logic and memory segment selection logic limits addresses to the least significant 16 bits of a possible 24 bit address. Different or alternate microcode program controlled instruction sequences with eliminated high order address clock cycles are used in the page zero mode.

Claims

1. A microcontroller, comprising:

a memory having a first address space with address words having a first number of bits; and

a computer coupled to said memory and comprising;

mode means for setting a mode of access of the first address space;

address means for restricting access of bits of the address words to a second number of bits less than the first number of bits of said address word in response to the mode set;

the second number of bits are lower order address bits of the address word;

said address means sets the upper order address bits of the address word to zero in a page zero mode; and

execution means for performing address operation using the second number of bits.

2. A microcontroller as recited in claim 1, wherein said execution means executes a program flow change instruction microcode program with a predetermined number of clock cycles in a normal mode and with a number of clock cycles less than the predetermined number in the page zero mode.

3. A microcontroller as recited in claim 1, wherein said execution means includes first and second sets of microcode programs, the second set being limited to low order address operations in the page zero mode.

4. A microcontroller, comprising:

a memory having a first address space; and

a computer coupled to said memory and comprising;

address means for restricting addresses to a second address space less than the first address space of said memory by holding and restricting stack location to the second address space upper order address bits at a zero value in a page zero mode; and

execution means for performing address operations limited to the second address space, executing a program flow change instruction microcode program with a predetermined number of clock cycles in a normal mode and with a number of clock cycles less than the predetermined number in the page zero mode and including first and second sets of microcode programs, the second set being limited to low order address operations in the page zero mode.

5. A method of performing a computer program, comprising:

determining whether a page zero mode is effective;

restricting computer program addresses to page zero when in the page zero mode; and

performing reduced clock cycle instructions when in the page zero mode;

wherein the reduced clock cycle instructions eliminate upper order address operations during microcode program execution of flow transfer instructions.

6. A microcontroller comprising:

a memory having an address space;

means for setting an access mode, said access mode being a page zero mode or a full mode;

means for determining the access mode set;

means for restricting access to the lower order address bits of the address words in the address space when in the page zero mode; and

means for setting the upper order address bits of the address word to zero in a page zero mode; and

means for allowing full access to all bits of the address words in the address space when in the full mode.

7. A processor comprising an execution unit, the execution unit comprising:

means for specifying at least first and second memory access mode values;

means for executing instructions using memory addresses having;

a first length in response to the first memory access mode value, and

a second length in response to the second memory access mode value, the first length being longer than the second length; and

in response to the second memory access mode value and an interrupt or exception, the execution unit stores a program counter having the second length; and

in response to the first memory access mode value and an interrupt or exception, the execution unit stores a program counter having the first length.

8. The processor of claim 7, wherein the means for specifying comprises a mode storage location.

9. The processor of claim 7 wherein

a. the first and second memory access mode values indicate whether a single page memory access mode is off or on, respectively;

b. the execution unit is arranged to be coupled to a memory organized into a plurality of pages, full addresses for the memory having the first length, addresses within a single page of the memory being specifiable with addresses of the second length.

10. The processor of claim 7 wherein selected types of the instructions specify addresses having

the first length in response to the first memory access mode value;

and

the second length, in response to the second memory access mode value.

11. The processor of claim 10, wherein the selected types require at least one less clock cycle to execute in response to the second memory access mode value than in response to the first memory access mode value.

12. The processor of claim 7, wherein the execution unit, responsive to an interrupt or exception,

forces a program counter to a predetermined value in response to the first memory access mode value;

and

skips such forcing in response to the second memory access mode value.