Method and apparatus for detecting and recovering from computer system malfunction

• US 6,012,154 A
• Filed: 09/18/1997
• Issued: 01/04/2000
• Est. Priority Date: 09/18/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Poisner, David I.
• Primary Examiner(s): WRIGHT, NORMAN M
• Application Number:
  US08/933,260
• Time in Patent Office: 838 Days
• Field of Search: 395/185.08, 395/185.04, 395/185.01, 395/184.01, 714/55, 714/51, 714/49, 714/47
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A timer is periodically reset by a software agent executing on a processor. If the timer is not reset within a predetermined period of time, an interrupt is generated. An interrupt handler then periodically resets the timer, and if the timer is not reset within an additional predetermined period of time, the computer system is partially reset.

Claims

1. A method, comprising the steps of:

periodically resetting a timer, the step of resetting the timer performed by a software agent executed on a processor;

triggering an interrupt if the timer is not reset within a predetermined period of time, the interrupt to indicate a malfunction;

executing an interrupt handler if the interrupt is triggered, the interrupt handler to cause the timer to be periodically reset, the interrupt handler to function independently of the software agent and the interrupt handler to attempt to cure the malfunction; and

performing at least a partial reset of the computer system if the timer is not reset by the interrupt handler within an additional predetermined period of time.

2. The method of claim 1 wherein the step of periodically resetting a timer includes executing an operating system-related software agent on a processor.

3. The method of claim 1 further comprising the step of initially loading the timer with a value stored in a register.

4. The method of claim 3 wherein the step of periodically resetting the timer includes the step of loading the timer with a value stored in a register.

5. The method of claim 4, wherein the step of executing an interrupt handler includes the step of loading the timer with a value stored in register.

6. The method of claim 1 further comprising the step of providing an indication accessible to the processor that the step of performing at least a partial reset of the computer system has been performed.

7. The method of claim 1 further comprising the step of fully resetting the computer system if the step of performing at least a partial reset of the computer system is not successful in curing the malfunction.

8. The method of claim 1 wherein the step of periodically resetting a timer includes periodically resetting a first timer, the step of triggering an interrupt includes triggering an interrupt if the first timer is not reset after a predetermined period of time, the step of executing an interrupt handler includes causing a second timer to be periodically reset, and the step of performing at least a partial reset of the computer system includes partially resetting the computer system if the second timer is not reset after a predetermined period of time.

9. A computer system, comprising:

a processor coupled to a bus;

a first storage area coupled to the bus, the first storage area to store an operating system-related software agent that when executed by the processor causes a first timer to be periodically reset;

circuitry for signaling an interrupt to the processor when the first timer is not reset after a predetermined period of time, the interrupt to indicate a malfunction;

a second storage area coupled to the bus, the second storage area to store an interrupt handler that functions independently of the operating system-related software agent, the interrupt handler to cause a second timer to be periodically reset when executed by the processor and the interrupt handler to attempt to cure the malfunction; and

circuitry for causing at least a partial system reset when the second timer is not reset after a predetermined period of time.

10. The system of claim 9 further comprising a flag for indicating that a partial system reset has occurred.

11. The system of claim 9 wherein the first and second timers are implemented as a single, reloadable timer.

12. The system of claim 11 further including circuitry for loading the reloadable timer with a value stored in a register.