Method for protecting important data bits using less important data bits

• US 6,012,160 A
• Filed: 10/03/1997
• Issued: 01/04/2000
• Est. Priority Date: 10/03/1997
• Status: Expired due to Term

• Current Assignee: Unwired Planet LLC (JP Morgan Chase & Co)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Dent, Paul W.
• Primary Examiner(s): Moise, Emmanuel L.
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US08/943,885
• Time in Patent Office: 823 Days
• Field of Search: 714/786, 714/790, 714/755, 714/739, 714/796
• US Class Current: 714/786
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/20 using signal quality detector

Abstract

A method and apparatus for protecting a first group of data bits using a second group of data bits within digital data transmissions is disclosed. First and second groups of data bits are encoded for transmission in a communication network. The second group of encoded data bits are scrambled using a scrambling mask generated from the first group of data bits. The first group of encoded data bits and the second group of encoded and scrambled data bits are then interleaved and transmitted to a receiver. The first group of data bits are decoded and used to regenerate the scrambling mask to descramble the second group of encoded and scrambled data bits. The second group of data bits may then be decoded. The results of the decoding of the second group of data bits are used to determine whether or not the first group of data bits were properly decoded.

Claims

1. An apparatus for coding information bits for transmission, comprising:

a separator for sorting the information bits into a first group of information bits and a second group of information bits;

a first convolutional encoder for coding the first group of information bits to produce a third group of coded information bits;

a second convolution encoder for coding the second group of information bits to produce a fourth group of coded information bits, wherein a ratio of the third group of information bits to the first group of information bits is greater than a ratio of the fourth group of information bits to the second group of information bits;

scrambling circuitry for scrambling the fourth group of coded information bits in dependence on the first group of information bits to produce a fifth group of scrambled, coded information bits; and

a transmitter for transmitting each of the fifth group of scrambled, coded information bits and each of the third group of coded information bits in a predetermined transmission sequence.

2. The apparatus of claim 1 wherein the scrambling circuitry further comprises a pseudorandom sequence generator for generating a sequence of scrambling bits from an initial group of bits dependent on the first group of information bits.

3. The apparatus of claim 2 wherein the sequence of scrambling bits contains a number of bits at least equal to the fourth number of coded information bits.

4. The apparatus of claim 3 wherein the scrambling bits are combined bitwise with corresponding bits of the fourth group of coded information bits to produce the fifth group of scrambled, coded information bits.

5. The apparatus of claim 3 wherein a first portion of the scrambling bits are combined bitwise with a corresponding first portion of the fourth group of coded information bits and a second portion of the scrambling bits define a scrambling order in which the fourth group of coded information bits are arranged.

6. The apparatus of claim 4 wherein the combining comprises an exclusive "or" operation.

7. The apparatus of claim 2 wherein the sequence of scrambling bits defines a scrambling order for rearranging the fourth group of coded information bits to produce the fifth group of scrambled, coded information bits.

8. The apparatus of claim 1 wherein the first convolutional encoder comprises a tailbiting convolutional encoders.

9. The apparatus of claim 1 wherein the second convolutional encoder comprises a tailbiting convolutional encoder.

10. The apparatus of claim 1 wherein the first convolutional encoder comprises a punctured convolutional encoder.

11. The apparatus of claim 1 wherein the second convolutional encoder comprises a punctured convolutional encoder.

12. The apparatus of claim 1 wherein the first and second convolutional encoders comprise:

a shift register including a number of memory elements;

logic circuitry for computing a plurality of logical combinations of contents of the memory elements of the shift register;

circuitry for initializing the memory elements to an initial state using a first portion of the first group of information bits;

a controller for sequentially shifting the first group and the second group of information bits through the memory elements of the shift register until the memory element returns to the initial state and for selecting prior to each shift a plurality of the logical combinations of the memory elements, the combinations dependant on whether the memory elements of the shift register contain only portions of the first group of information bits or the second group of information bits, the logical combinations comprising the third and the fourth groups of coded information bits.

13. The apparatus of claim 12 wherein the selection of logical combinations for each shift varies according to a predetermined puncturing schedule.

14. An apparatus for receiving a signal and decoding therefrom coded and scrambled information bits to produce a first and a second group of information bits, comprising:

a first processor for hypothesizing in dependence on a metric value a plurality of first sequences of bits containing the first group of information bits to determine a first sequence of bits with a cumulative metric indicative of a highest likelihood;

a first re-encoder for re-encoding the hypothesized plurality of first sequences of bits to produce first expected signal samples corresponding to the first group of information bits;

a first metric accumulator for comparing the first expected signal samples with a corresponding received signal samples and for accumulating a cumulative metric associated with the first expected signal samples based on the comparison;

unscrambling circuitry for unscrambling the received signal samples corresponding to a second group of information bits based on the determined first group of information bits of highest likelihood;

a second processor for successively hypothesizing a second bit sequence containing the second group of information bits dependant on a plurality of stored metric values to determine the second bit sequence having a second cumulative metric indicative of a highest likelihood;

a second re-encoder for re-encoding the hypothesized second bit sequence to produce a sequence of second expected signal samples corresponding to a second group of information bits;

a second metric accumulator for comparing unscrambled received signal to the sequence of second expected signal samples and for accumulating a plurality of second cumulative metrics based on the comparisons; and

error indicating circuitry for processing the first cumulative metric indicating highest likelihood with the second cumulative metric indicating highest likelihood to produce an error indicator signal.

15. The apparatus of claim 14 wherein the first re-encoder and second re-encoders comprise convolutional encoders.

16. The apparatus of claim 14 wherein the first and second re-encoders comprise tailbiting convolutional encoders.

17. The apparatus of claim 14 where the first and second re-encoders comprise punctured convolutional encoders.

18. The apparatus of claim 14 wherein the first re-encoder produces a number of expected signal samples having a first ratio to the first group of information bits and the second re-encoder produce a number of expected signal samples having a second ratio to the second group of information bits, wherein the second ratio is lower than second first ratio.

19. The apparatus of claim 14 wherein the unscrambling circuitry further comprises a generator for generating an unscrambling bit sequence from an initial state dependent on the determined first bit sequence of highest likelihood.

20. The apparatus of claim 19 wherein the unscrambling bit sequence determines an order for comparison of the received signal with the expected signal samples by the second metric accumulator.

21. The apparatus of claim 14 where the unscrambling bit sequence comprises at least the same number of bits as the signal samples compared by the second metric accumulation means.

22. The apparatus of claim 21, wherein the means for unscrambling combines each bit of the bit scrambling sequence with a corresponding received signal sample.

23. The apparatus of claim 14 wherein the error indicating circuitry further additively combines the first and the second cumulative metrics and compares the sum with a threshold value to produce the error indicator signal.

24. The apparatus of claim 14 wherein the error indicator circuitry measures the average signal strength of received signal samples.

25. The apparatus of claim 24 wherein the average signal strengths are computed by the first and the second metric accumulators.

26. The apparatus of claim 24 wherein the average signal strengths comprise a root-mean-square measure.

27. The apparatus of claim 14 wherein the error indicator circuitry normalizes the metrics by dividing by a respective average signal strength.

28. The apparatus of claim 27 wherein the normalized metrics define a two-dimensional plane and the error indicator signal depends on whether the signal lies within a first or second region of the plane.

29. An apparatus for receiving a signal and decoding therefrom coded and scrambled information bits to produce a first group of decoded information bits corrected for transmission errors plus an indicator signal warning of the likelihood of uncorrected errors and a second group of information bits corrected for some transmission errors, comprising:

a first processor for successively hypothesizing first sequences of bits containing said first group of information bits in dependence on metric values to determine a first sequence of bits having a first cumulative metric indicative of highest likelihood;

a first re-encoder for re-encoding said hypothesized first sequences of bits to produce sequences of first expected signal samples corresponding to said first group of information bits;

a first metric accumulator for comparing said first expected signal samples with corresponding received signal samples and accumulating said cumulative metrics based on similarity or difference;

a second processor for successively hypothesizing second sequences containing said second group of information bits in dependence on metric values to determine a second sequence of bits having a second cumulative metric indicative of highest likelihood;

a second re-encoder for re-encoding said hypothesized second sequence of bits to produce a sequence of second expected signal samples corresponding to said second group of information bits;

scrambling circuitry for scrambling said second expected signal samples corresponding to said second group of information bits using said determined first sequence of information bits of highest likelihood;

a second metric accumulator for comparing said received signal samples with said scrambled expected signal samples and accumulating said second cumulative metrics based on similarity or difference; and

error indicator circuitry for processing said first cumulative metric indicative of highest likelihood with said second cumulative metric indicative of highest likelihood to produce said indicator signal.

30. A method for encoding information bits comprising the steps of:

sorting information bits into a first group of bits and a second group of bits;

selecting a first number of adjacent bits within the first group of bits and the second group of bits including only bits of the first group;

calculating a first number of coded bits from the first number of adjacent bits;

selecting a second number of adjacent bits from the first group of bits and the second group of bits including only bits of the second group;

calculating a second number of coded bits from the second number of adjacent bits; and

scrambling said second number of coded bits in dependence on the first number of coded bits to produce a third group of coded bits.

31. The method of claim 30 wherein the step of scrambling further comprises the steps of:

generating a scrambling mask dependent on the first group of bits; and

adding the scrambling mask to the second group of coded bits.

32. A method for decoding a coded information signal containing a first set of coded symbols corresponding to a first set of information symbols and a second set of scrambled and coded symbols corresponding to a second set of information symbols, comprising the steps of:

processing a first portion of the coded information signal containing the first set of coded symbols to generate a number of hypotheses for the first set of information symbols and an associated likelihood metric;

processing a second portion of the coded information signal containing the second set of scrambled and coded symbols using the number of hypotheses for the first set of information symbols to unscramble and decode the scrambled and coded symbols and to compute an updated likelihood metric; and

selecting one of the number of hypotheses with a highest likelihood metric and extracting the first and second sets of information symbols therefrom as desired decoded symbols when the one of the hypotheses has been extended to include all of the first and second set of information symbols.