LDD transistor using novel gate trim technique

• US 6,013,570 A
• Filed: 07/17/1998
• Issued: 01/11/2000
• Est. Priority Date: 07/17/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheung, Patrick K., Steffan, Paul J., Yu, Allen S.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MAI, ANH D
• Application Number:
  US09/118,389
• Time in Patent Office: 543 Days
• Field of Search: 438/159, 438/163, 438/174, 438/194-196, 438/201, 438/202, 438/217, 438/230-232, 438/179, 438/182, 438/184, 438/301, 438/303, 438/585, 438/595, 438/574
• US Class Current: 438/595
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and the second mask layer are patterned to form first gate mask and second gate mask respectively. The polysilicon gate is then formed by anisotropically etching the polysilicon layer. The second gate mask is then removed. The polysilicon gate is then etched isotropically to reduce its width using the gate oxide layer and the patterned first gate mask as hard masks. The first gate mask is then used as a mask for dopant implantation to form source and drain extensions which are spaced away from the edges of the polysilicon gate. Thereafter, the first gate mask is removed and a spacer is formed dopant implantation to form deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the source and drain extension junctions and junctions, and the spacer is removed. Since the source and drain extension junctions are spaced away from the edges of the polysilicon gate, the displacement of the source/drain extension junctions into the channel is reduced. This results in a device with reduced parasitic capacitance.

Claims

1. A method for manufacturing a semiconductor on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;

forming a polysilicon layer over said gate oxide layer;

forming a first mask layer over said polysilicon layer;

forming a second mask layer over said first mask layer;

patterning said second mask layer to form second gate masks;

patterning said first mask layer to form first gate masks after the step of patterning said second mask layer to form second gate masks;

anisotropically etching said polysilicon layer to form polysilicon gates;

removing said second gate masks;

isotropically etching said polysilicon gates prior to the step of removing said first gate masks;

implanting shallow extension junctions with a dopant after the step of isotropically etching said polysilicon gates;

removing said first gate masks;

forming sidewall spacers around said polysilicon gates after the step of removing said first gate masks; and

implanting deep junctions with said dopant.

2. The method as claimed in claim 1 wherein the step of isotropically etching said polysilicon gates results in the removal of portions of said polysilicon gates in a lateral direction by a predetermined amount.

3. The method as claimed in claim 1 wherein said first mask layer is a material selected from the group consisting of oxide and nitride.

4. The method as claimed in claim 1 wherein said first mask layer is silicon oxynitride.