Semiconductor device having interlayer insulating film and method for forming the same

• US 6,013,928 A
• Filed: 06/07/1995
• Issued: 01/11/2000
• Est. Priority Date: 08/23/1991
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hiroki, Masaaki, Mase, Akira, Takemura, Yasuhiko, Uochi, Hideki, Yamazaki, Shunpei, Zhang, Hongyong, Nemoto, Hideki
• Primary Examiner(s): Hardy, David B.
• Assistant Examiner(s): Wilson, Allan R.
• Application Number:
  US08/479,393
• Time in Patent Office: 1,679 Days
• Field of Search: 257/59, 257/60, 257/61, 257/66, 257/72, 257/394, 257/372, 257/67, 257/49, 257/51, 257/52, 257/53, 257/57, 257/69, 257/70, 257/74, 257/75, 257/347, 257/348, 257/349, 257/350, 257/351 , 257/352, 257/353, 257/354, 257/336, 257/344, 257/408, 359/69, 359/54, 359/87, 359/88
• US Class Current: 257/347
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H04N 3/127 using liquid crystals

Abstract

An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Claims

1. A liquid crystal display device comprising:

a pixel electrode;

at least one thin film transistor for switching said pixel electrode;

a liquid crystal layer adjacent to said pixel electrode,

said thin film transistor comprising;

a crystalline semiconductor layer formed on an insulating surface;

a first pair of impurity regions formed in said crystalline semiconductor layer wherein said first pair of impurity regions are doped with an impurity having one conductivity type at a first concentration;

a channel region formed in said crystalline semiconductor layer between said pair of impurity regions;

a second pair of impurity regions formed between said first pair of impurity regions and said channel region wherein said second pair of impurity regions are doped with an impurity having said conductivity type at a second concentration smaller than said first concentration;

a gate electrode adjacent to said channel region with a gate insulating film interposed therebetween;

an interlayer insulating film formed over said crystalline semiconductor layer;

an organic resin film formed over said interlayer insulating film, said organic resin film having a leveled upper surface;

a pixel electrode formed over said organic resin film.

2. A device according to claim 1 wherein said second pair of impurity regions have a same conductivity type as said first pair of impurity regions.

3. A device according to claim 1 wherein said crystalline semiconductor layer has a hole mobility not lower than 10 cm² /Vsec or an electron mobility not lower than 15 cm² /Vsec.

4. A device according to claim 1 wherein said gate electrode comprises a material selected from the group consisting of Ti, Al, Ta, Cr and Si.

5. A device according to claim 1 wherein said interlayer insulating film comprises silicon oxide.

6. A device according to claim 1 wherein said pixel electrode is transparent.

7. A device according to claim 1 wherein said interlayer insulating film has a thickness within a range from 0.2 to 0.6 μ

m.

8. A device according to claim 1 wherein said thin film transistor is a top-gate type transistor.

9. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a larger band gap than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a planarizing film comprising an organic resin formed over said interlayer insulating film; and

a pixel electrode formed over said planarizing film and electrically connected to said thin film transistor through a hole of said planarizing film.

10. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a lower crystallinity than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a planarizing film comprising an organic resin formed over said interlayer insulating film; and

a pixel electrode formed over said planarizing film and electrically connected to said thin film transistor through a hole of said planarizing film.

11. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions contain a dopant impurity at a lower concentration than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said second contact hole does not overlap said first contact hole.

12. A device according to claim 11 wherein said conductive layer comprises aluminum.

13. A device according to claim 11 wherein said gate electrode is located over said channel forming region.

14. A device according to claim 11 wherein said interlayer insulating film comprises silicon oxide.

15. A device according to claim 11 wherein said planarizing film comprises polyimide.

16. A device according to claim 11 wherein said crystalline semiconductor layer has a hole mobility not lower than 10 cm² /Vsec or an electron mobility not lower than 15 cm² /Vsec.

17. A device according to claim 11 wherein said gate electrode comprises a material selected from the group consisting of Ti, Al, Ta, Cr and Si.

18. A device according to claim 11 wherein said pixel electrode is transparent.

19. A device according to claim 11 wherein said interlayer insulating film has a thickness within a range from 0.2 to 0.6 μ

m.

20. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a larger band gap than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said second contact hole does not overlap said first contact hole.

21. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a lower crystallinity than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said second contact hole does not overlap said first contact hole.

22. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions contain a dopant impurity at a lower concentration than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said conductive layer has an extended portion which extends from said first contact hole and said pixel electrode contacts said extended portion.

23. A device according to claim 22 wherein said conductive layer comprises aluminum.

24. A device according to claim 22 wherein said gate electrode is located over said channel forming region.

25. A device according to claim 22 wherein said interlayer insulating film comprises silicon oxide.

26. A device according to claim 22 wherein said planarizing film comprises polyimide.

27. A device according to claim 22 wherein said crystalline semiconductor layer has a hole mobility not lower than 10 cm² /Vsec or an electron mobility not lower than 15 cm² /Vsec.

28. A device according to claim 22 wherein said pixel electrode is transparent.

29. A device according to claim 22 wherein said interlayer insulating film has a thickness within a range from 0.2 to 0.6 μ

m.

30. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a larger band gap than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said conductive layer has an extended portion which extends from said first contact hole and said pixel electrode contacts said extended portion.

31. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a lower crystallinity than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said conductive layer has an extended portion which extends from said first contact hole and said pixel electrode contacts said extended portion.

32. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said second contact hole does not overlap said first contact hole.

33. A device according to claim 32 wherein said conductive layer comprises aluminum.

34. A device according to claim 32 wherein said gate electrode is located over said channel forming region.

35. A device according to claim 32 wherein said interlayer insulating film comprises silicon oxide.

36. A device according to claim 32 wherein said planarizing film comprises polyimide.

37. A device according to claim 32 wherein said crystalline semiconductor layer has a hole mobility not lower than 10 cm² /Vsec or an electron mobility not lower than 15 cm² /Vsec.

38. A device according to claim 32 wherein said gate electrode comprises a material selected from the group consisting of Ti, Al, Ta, Cr and Si.

39. A device according to claim 32 wherein said pixel electrode is transparent.

40. A device according to claim 32 wherein said interlayer insulating film has a thickness within a range from 0.2 to 0.6 μ

m.

41. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said conductive layer has an extended portion which extends from said first contact hole and said pixel electrode contacts said extended portion.

42. A device according to claim 41 wherein said conductive layer comprises aluminum.

43. A device according to claim 41 wherein said gate electrode is located over said channel forming region.

44. A device according to claim 41 wherein said interlayer insulating film comprises silicon oxide.

45. A device according to claim 41 wherein said planarizing film comprises polyimide.

46. A device according to claim 41 wherein said crystalline semiconductor layer has a hole mobility not lower than 10 cm² /Vsec or an electron mobility not lower than 15 cm² /Vsec.

47. A device according to claim 41 wherein said pixel electrode is transparent.

48. A device according to claim 41 wherein said interlayer insulating film has a thickness within a range from 0.2 to 0.6 μ

m.

49. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions contain a dopant impurity at a lower concentration than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said channel forming region is doped with boron at a concentration of 1×

10¹⁵ to 1×

10¹⁸ atoms/cm³.

50. A device according to claim 49 wherein said conductive layer comprises aluminum.

51. A device according to claim 49 wherein said gate electrode is located over said channel forming region.

52. A device according to claim 49 wherein said interlayer insulating film comprises silicon oxide.

53. A device according to claim 49 wherein said planarizing film comprises polyimide.

54. A device according to claim 49 wherein said crystalline semiconductor layer has a hole mobility not lower than 10 cm² /Vsec or an electron mobility not lower than 15 cm² /Vsec.

55. A device according to claim 49 wherein said gate electrode comprises a material selected from the group consisting of Ti, Al, Ta, Cr and Si.

56. A device according to claim 49 wherein said pixel electrode is transparent.

57. A device according to claim 49 wherein said interlayer insulating film has a thickness within a range from 0.2 to 0.6 μ

m.

58. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a larger band gap than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said channel forming region is doped with boron at a concentration of 1×

10¹⁵ to 1×

10¹⁸ atoms/cm³.

59. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a lower crystallinity than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said channel forming region is doped with boron at a concentration of 1×

10¹⁵ to 1×

10¹⁸ atoms/cm³.

60. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions contain a dopant impurity at a lower concentration than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said semiconductor island exhibits a peak of Raman spectroscopy shifted toward lower frequency side from 522 cm^-1.

61. A device according to claim 60 wherein said conductive layer comprises aluminum.

62. A device according to claim 60 wherein said gate electrode is located over said channel forming region.

63. A device according to claim 60 wherein said interlayer insulating film comprises silicon oxide.

64. A device according to claim 60 wherein said planarizing film comprises polyimide.

65. A device according to claim 60 wherein said crystalline semiconductor layer has a hole mobility not lower than 10 cm² /Vsec or an electron mobility not lower than 15 cm² /Vsec.

66. A device according to claim 60 wherein said gate electrode comprises a material selected from the group consisting of Ti, Al, Ta, Cr and Si.

67. A device according to claim 60 wherein said pixel electrode is transparent.

68. A device according to claim 60 wherein said interlayer insulating film has a thickness within a range from 0.2 to 0.6 μ

m.

69. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a larger band gap than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said semiconductor island exhibits a peak of Raman spectroscopy shifted toward lower frequency side from 522 cm^-1.

70. An active matrix device comprising:

a substrate having an insulating surface;

a thin film transistor formed over said substrate wherein said thin film transistor comprises;

a semiconductor island comprising crystalline silicon;

a channel forming region in said semiconductor island;

source and drain regions formed in said semiconductor island with said channel forming region interposed therebetween;

a pair of impurity regions disposed between said source and drain regions and said channel forming region wherein said pair of impurity regions have a lower crystallinity than said source and drain regions; and

a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween;

an interlayer insulating film covering said thin film transistor;

a conductive layer formed on said interlayer insulating film and connected to one of the source or drain regions of said thin film transistor through a first contact hole of said interlayer insulating film;

a planarizing film comprising an organic resin formed over said interlayer insulating film and said conductive layer; and

a pixel electrode formed over said planarizing film and connected to said conductive layer through a second contact hole of said planarizing film,

wherein said semiconductor island exhibits a peak of Raman spectroscopy shifted toward lower frequency side from 522 cm^-1.