Stackable chip scale semiconductor package with mating contacts on opposed surfaces

• US 6,013,948 A
• Filed: 04/01/1998
• Issued: 01/11/2000
• Est. Priority Date: 11/27/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Wood, Alan G., Farnworth, Warren M.
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US09/053,274
• Time in Patent Office: 650 Days
• Field of Search: 257/698, 257/666, 257/673, 257/679, 257/686, 257/693, 257/737, 257/738, 257/734, 257/778, 257/787, 257/736, 257/723, 257/682, 257/685, 257/774
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49883 : the conductive materials containing organic materials or pastes, e.g. for thick films for printed circuits H05K1/092
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.

Claims

1. A stackable semiconductor package comprising:

a substrate comprising silicon and having a first surface and an opposing second surface;

a plurality of first contacts on the first surface and a plurality of second contacts on the second surface, the first contacts and the second contacts having a matching pattern and mating configurations, the first contacts or the second contacts comprising a conductive polymer;

a semiconductor die mounted to the substrate comprising a plurality of die contacts in electrical communication with the first contacts or the second contacts; and

a plurality of conductive vias in the substrate electrically connecting the first contacts to the second contacts;

the semiconductor package configured for stacking on a substantially identical second semiconductor package comprising third contacts bonded to the first contacts.

2. The package of claim 1 wherein the third contacts comprise bumps and the second contacts comprise recesses configured to retain the third contacts.

3. The package of claim 1 wherein the third contacts comprise cylindrical tip portions and the second contacts comprise openings configured to retain the third contacts.

4. The package of claim 1 wherein the conductive polymer comprises a material selected from the group consisting of isotropic adhesives and anisotropic adhesives.

5. A stackable semiconductor package comprising:

a semiconductor die comprising a plurality of die contacts;

a silicon substrate comprising a first surface, an opposing second surface, a cavity for mounting the die and a curable polymer within the cavity at least partially encapsulating the die;

a plurality of first contacts on the first surface and a plurality of second contacts on the second surface, the first contacts and the second contacts having a matching pattern and mating configurations, and either the first contacts or the second contacts in electrical communication with the die contacts; and

a plurality of conductive vias in the substrate electrically connecting the first contacts to the second contacts;

the semiconductor package configured for stacking on a substantially identical second semiconductor package comprising third contacts bonded to the first contacts.

6. A stackable semiconductor package comprising:

a substrate comprising a first surface, an opposing second surface, and a cavity;

a plurality of first contacts on the first surface;

a plurality of second contacts on the second surface, the second contacts configured for electrically engaging third contacts substantially identical to the first contacts on a second semiconductor package substantially identical to the semiconductor package;

a plurality of conductive vias in the substrate electrically connecting the first contacts to the second contacts; and

a semiconductor die comprising a plurality of die contacts, the die mounted to the cavity at least partially encapsulated in a polymer within the cavity with the die contacts in electrical communication with the first contacts or the second contacts.

7. The package of claim 6 wherein the substrate comprises silicon and the conductive vias comprise electrically insulated openings at least partially filled with a conductive material.

8. A stackable semiconductor package comprising:

a substrate comprising a first surface and an opposing second surface;

a plurality of first contacts comprising bumps on the first surface;

a plurality of second contacts comprising recesses on the second surface, the second contacts configured for retaining and electrically engaging third contacts substantially identical to the first contacts on a second semiconductor package substantially identical to the semiconductor package;

the first contacts or the second contacts comprising a conductive polymer;

a plurality of conductive vias in the substrate electrically connecting the first contacts to the second contacts; and

a semiconductor die comprising a plurality of die contacts, the die mounted to the substrate with the die contacts in electrical communication with the first contacts or the second contacts.

9. The package of claim 8 wherein the substrate comprises silicon and the conductive vias comprise openings having an insulating layer formed on an inside diameter thereof, and at least partially filled with a conductive material.

10. A stackable semiconductor package comprising:

a silicon substrate comprising a plurality of first contacts on a first surface thereof, and a plurality of second contacts on a second surface thereof, the second contacts sized and shaped to retain and electrically engage third contacts substantially identical to the first contacts on a second semiconductor package substantially identical to the first semiconductor package;

an opening in the substrate;

a semiconductor die on the substrate and comprising a plurality of die contacts;

a pattern of conductors on the second surface in electrical communication with the second contacts;

a plurality of wires extending through the opening and bonded to the die contacts and to the conductors; and

a plurality of electrical insulated conductive vias in the substrate in electrical communication with the first contacts and with the second contacts.

11. The package of claim 10 wherein the first contacts comprise cylindrical portions and the second contacts comprise circular openings sized to receive the third contacts.

12. The package of claim 10 wherein the first contacts comprise bumps and the second contacts comprise recesses.

13. A stackable semiconductor package comprising:

a substrate comprising a first surface, an opposing second surface, and a die mounting site;

a plurality of first contacts on the first surface comprising a conductive polymer;

a semiconductor die mounted proximate to the die mounting site and comprising a plurality of die contacts in electrical communication with the first contacts or the second contacts; and

a plurality of conductive vias in the substrate comprising openings with a conductive layer thereon configured to retain and electrically engage second contacts substantially identical to the first contacts on a second package substantially identical to the semiconductor package.

14. The package of claim 13 wherein the substrate comprises silicon and the openings comprise an electrically insulating layer.

15. The package of claim 13 wherein the first contacts comprise balls with a cylindrical tip portion.

16. A stackable semiconductor package comprising:

a silicon substrate comprising a first surface and an opposing second surface;

a plurality of first contacts on the first surface having a first pattern;

a plurality of second contacts on the second surface having a second pattern matching the first pattern, the second contacts comprising a conductive polymer layer configured for mating electrical engagement and bonding with third contacts substantially identical to the first contacts on a second semiconductor package substantially identical to the semiconductor package;

a plurality of conductors on the first surface or the second surface in electrical communication with the first contacts or the second contacts;

a semiconductor die mounted to the substrate comprising a plurality of die contacts in electrical communication with the conductors; and

a plurality of conductive vias in the substrate electrically connecting the first contacts to the second contacts, the conductive vias comprising electrically insulated vias at least partially filled with conductive material.

17. The package of claim 16 wherein the first contacts comprise a conductive polymer.

18. The package of claim 16 wherein the first contacts comprise bumps.

19. The package of claim 16 wherein the conductive vias comprise an SiO₂ insulating layer.

20. The package of claim 16 wherein the conductive vias comprise a conductive polymer.

21. An electronic assembly comprising:

a supporting substrate;

a first semiconductor package mounted to the supporting substrate comprising a first silicon substrate, a first contact formed on a first surface of the first substrate comprising a conductive polymer, a second contact formed on an opposing second surface of the first substrate, and an electrically insulated conductive via in the first substrate electrically connecting the first contact to the second contact; and

a second semiconductor package stacked on the first semiconductor package, the second semiconductor package substantially identical to the first semiconductor package and comprising a third contact substantially identical to the first contact sized and shaped to retain and electrically engage the second contact on the first package.

22. The assembly of claim 21 wherein the first contact comprises a bump and the second contact comprises a recess.

23. The assembly of claim 21 wherein the first contact comprises a substantially cylindrical tip portion and the second contacts comprises an opening sized to receive the tip portion.

24. An electronic assembly comprising:

a supporting substrate;

a first semiconductor package on the supporting substrate comprising;

a silicon substrate comprising a first surface and an opposing second surface;

a plurality of first contacts on the first surface and a plurality of second contacts on the second surface, the first contacts and the second contacts comprising a conductive polymer;

a semiconductor die on the substrate comprising a plurality of die contacts in electrical communication with the first contacts or the second contacts;

a plurality of electrically insulated conductive vias in the substrate electrically connecting the first contacts to the second contacts;

a second semiconductor package substantially identical to the first semiconductor package stacked on the first semiconductor package, and comprising a plurality of third contacts substantially identical to the second contacts and configured to retain and electrically engage the second contacts.

25. The assembly of claim 24 wherein the conductive vias comprise an insulating layer and a conductive material formed therein.

26. The assembly of claim 24 wherein the first contacts and the second contacts comprise an isotropic adhesive.

27. The assembly of claim 24 wherein the first contacts and the second contacts comprise an anisotropic adhesive.