Micro probe ring assembly and method of fabrication

• US 6,014,032 A
• Filed: 09/30/1997
• Issued: 01/11/2000
• Est. Priority Date: 09/30/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Vallett, David Paul, Palagonia, Anthony Michael, Pikna, Paul Joseph, Maddix, John Thomas
• Primary Examiner(s): Do, Diep N.
• Application Number:
  US08/940,915
• Time in Patent Office: 833 Days
• Field of Search: 324/762, 324/754, 324/757, 324/72.5, 29/842, 29/843
• US Class Current: 324/750.26
• CPC Class Codes: G01R 1/06711 Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card

Abstract

A multi-probe ring assembly including integral fine probe tips, conductive lines with terminal connection for testing semiconductor devices and a method of construction of the multi-probe ring assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe points. Semiconductor machining processes are used to complete the probe ring assembly.

Claims

1. A multi-tipped monolithic probe ring assembly for use in testing apparatus for contacting a predetermined target on a semiconductor device comprising:

a supporting substrate bonded to a monolithic insulator, said monolithic insulator having a thick region, a thin region and a sloped region between said thick and thin regions;

a plurality of conductive lines, each having a tip portion positioned on said thick region of said monolithic insulator, wherein said tip portions comprise raised fine points integral to each conductive line and arranged in a pattern aligned to predetermined portions of a semiconductor device, an intermediate portion positioned on the sloped region of said monolithic insulator, and a terminal end portion positioned on said thin region of said monolithic insulator; and

means for contacting said terminal end.

2. The multi-tipped monolithic probe assembly of claim 1, further comprising a conductive shield between said conductive tip portions of said conductive lines.

3. The multi-tipped monolithic probe assembly of claim 1, wherein a first set of said tip portions are adapted to testing a first region of said predetermined target at a first height on said semiconductor device and a second set of said tip portions are adapted to testing a second region of said predetermined target at a second height on said semiconductor device, the second height being different from the first height.

4. The multi-tipped monolithic probe assembly of claim 3, further comprising a conductive shield between said conductive tip portions of said conductive lines.

5. A multi-tipped monolithic probe ring assembly for use in testing apparatus for contacting a predetermined target on a semiconductor device comprising:

a supporting substrate bonded to a monolithic insulator, said monolithic insulator having a thick region, a thin region and a sloped region between said thick and thin regions;

an upper conductive shield layer on said thin region of said insulator and a upper dielectric layer on said upper conductive shield layer;

a plurality of conductive lines, each having a tip portion positioned on said thick region of said monolithic insulator, wherein said tip portions comprise raised fine points integral to each conductive line and arranged in a pattern aligned to predetermined portions of a semiconductor device, an intermediate portion positioned on the sloped region of said monolithic insulator, and a terminal end portion positioned on said upper dielectric layer;

a lower conductive shield layer and a lower dielectric layer, said lower dielectric between said upper shield layer and said conductive lines; and

means for contacting said terminal end.

6. A multi-tipped monolithic probe ring assembly for use in testing apparatus for contacting a predetermined target on a semiconductor device comprising:

a supporting substrate bonded to a monolithic insulator, said monolithic insulator having a thick region, a thin region and a sloped region between said thick and thin regions;

a first upper conductive shield layer on said thin region of said insulator and a first upper dielectric layer on said first upper conductive shield layer;

a second upper conductive shield layer on said first upper dielectric layer and a second upper dielectric layer on said second upper conductive shield layer;

a plurality of conductive lines, each having a tip portion positioned on said thick region of said monolithic insulator, wherein said tip portions comprise raised fine points integral to each conductive line and arranged in a pattern aligned to predetermined portions of a semiconductor device, an intermediate portion positioned on the sloped region of said monolithic insulator, and a terminal end portion positioned on said second upper dielectric layer;

a first lower dielectric layer on said conductive lines, a first lower conductive shield layer on said first lower dielectric layer, a second lower conductive shield layer on said first lower dielectric layer, and a second lower dielectric layer on said second lower conductive shield layer; and

means for contacting said terminal end.