Apparatus for providing improved encryption protection in a communication system

• US 6,014,446 A
• Filed: 11/25/1997
• Issued: 01/11/2000
• Est. Priority Date: 02/24/1995
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Finkelstein, Louis David
• Primary Examiner(s): Barron, Jr., Gilberto
• Application Number:
  US08/977,769
• Time in Patent Office: 777 Days
• Field of Search: 380/42, 380/43, 380/44, 380/46, 708/252
• US Class Current: 380/46
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0668 producing a non-linear pseudorandom sequence
• CPC Class Codes: H04L 9/12 Transmitting and receiving encryption devices synchronised or initially set up in a particular manner

Abstract

An encryption apparatus and method generate a unique keystream output value for every frame of bearer traffic to provide encryption protection in a communications system. The keystream output value is generated from the following equations:

x(n+1).sub.low ={x(n).sub.low *R1.sub.low +R2.sub.low } mod R3.sub.low

x(n+1).sub.high ={x(n).sub.high *R2.sub.high +R1.sub.high } mod R3.sub.high

where R1, R2, and R3 are linear feedback shift registers and x(n) and x(n+1) represent previous and current output values.

Claims

1. An encryption method for generating a unique keystream output value for every frame of bearer traffic to provide an output from a combination of x(n+1)_low and x(n+1)_high in accordance with equations of a form:

space="preserve" listing-type="equation">x(n+1).sub.low ={x(n).sub.low *R1.sub.low +R2.sub.low } mod R3.sub.low

space="preserve" listing-type="equation">x(n+1).sub.high ={x(n).sub.high *R2.sub.high +R1.sub.high } mod R3.sub.high

where R1, R2, and R3 are linear feedback shift registers, R4 is a shift control register coupled to a clock utilized for tap configuration control of R1, R2 and R3, and values x(n) and x(n+1) represent previous and current output values, the encryption method comprising the steps of;

initializing R1, R2, R3 and R4 according to a predetermined scheme;

generating the output by operating on one of;

a first and second predetermined selection of bits of registers R1, R2, and R3; and

where the first selection of bits are represented by Rx_low and the second selection of bits are represented by Rx_high, respectively, where x=1, 2, 3;

setting a two most significant bits of the first selection of bits and of the second selection of bits in register R3 to `11`;

processing x(n+1) in separate low and high bit portions, wherein the low and high bit portions are determined by computing;

space="preserve" listing-type="equation">x(n+1).sub.low ={x(n).sub.low *R1.sub.low +R2.sub.low } mod R3.sub.low

space="preserve" listing-type="equation">x(n+1).sub.high ={x(n).sub.high *R2.sub.high +R1.sub.high } mod R3.sub.high

then rotating the low portion a first predetermined number of bits, and the high portion a second predetermined number of bits and producing a keystream output value by a logic exclusive-OR operation on rotated high and low portions.

2. The method of claim 1 wherein the low portion is rotated 3 bits to the left, and the high portion is rotated 3 bits to the right.

3. An encryption device for generating a unique keystream output value for every frame of bearer traffic to provide an output from a combination of x(n+1)_low and x(n+1)_high in accordance with equations of a form:

space="preserve" listing-type="equation">x(n+1).sub.low ={x(n).sub.low *R1.sub.low +R2.sub.low } mod R3.sub.low

space="preserve" listing-type="equation">x(n+1).sub.high ={x(n).sub.high *R2.sub.high +R1.sub.high } mod R3.sub.high

where R1, R2, and R3 are linear feedback shift registers, R4 is a shift control register coupled to a clock utilized for tap configuration control of R1, R2 and R3, and values x(n) and x(n+1) represent previous and current output values, the encryption device comprising;

three linear feedback shift registers R1, R2, and R3, each coupled to a separate switch and a fourth linear feedback shift register R4 to provide alternate tap configurations to an logical exclusive-OR unit that provides an logical exclusive-OR output wherein a clock is coupled to R4 and to a summer that is coupled to R1, R2 and R3, wherein R4 and the switch are utilized to select a tap configuration, and R1, R2, R3 and R4 are initialized prior to each output determination according to a predetermined scheme,

wherein the R1, R2, and R3 generate an output by operating on one of a first and second predetermined selection of bits of registers R1, R2, and R3; and

where the first selection of bits are represented by Rx_low and the second selection of bits are represented by RX_high, respectively, where x=1, 2, 3;

a two most significant bits of the first selection of bits and of the second selection of bits in register R3 are set to `11`;

x(n+1) is processed in separate low and high bit portions, wherein the low and high bit portions are determined by computing;

space="preserve" listing-type="equation">x(n+1).sub.low ={x(n).sub.low *R1.sub.low +R2.sub.low } mod R3.sub.low

space="preserve" listing-type="equation">x(n+1).sub.high ={x(n).sub.high *R2.sub.high +R1.sub.high } mod R3.sub.high

then rotating the low portion a first predetermined number of bits, and the high portion a second predetermined number of bits and producing a keystream output value by a logical exclusive-OR operation on rotated high and low portions.

4. The encryption device of claim 3 wherein the low portion is rotated 3 bits to the left, and the high portion is rotated 3 bits to the right.

5. A computer usable medium/memory having computer readable program code means thereon comprising:

means for generating a unique keystream output value for every frame of bearer traffic to provide an output from a combination of x(n+1)_low and x(n+1)_high in accordance with equations of a form;

space="preserve" listing-type="equation">x(n+1).sub.low ={x(n).sub.low *R1.sub.low +R2.sub.low } mod R3.sub.low

space="preserve" listing-type="equation">x(n+1).sub.high ={x(n).sub.high *R2.sub.high +R1.sub.high } mod R3.sub.high

where R1, R2, and R3 are linear feedback shift registers, R4 is a shift control register coupled to a clock utilized for tap configuration control of R1, R2 and R3, and values x(n) and x(n+1) represent previous and current output values, the computer readable program code means including the steps of;

initializing R1, R2, R3 and R4 according to a predetermined scheme;

generating the output by operating on one of;

a first and second predetermined selection of bits of registers R1, R2, and R3; and

where the first selection of bits are represented by Rx_low and the second selection of bits are represented by Rx_high, respectively, where x=1, 2, 3;

setting a two most significant bits of the first selection of bits and of the second selection of bits in register R3 to `11`;

processing x(n+1) in separate low and high bit portions, wherein the low and high bit portions are determined by computing;

space="preserve" listing-type="equation">x(n+1).sub.low ={x(n).sub.low *R1.sub.low +R2.sub.low } mod R3.sub.low

space="preserve" listing-type="equation">x(n+1).sub.high ={x(n).sub.high *R2.sub.high +R1.sub.high } mod R3.sub.high

then rotating the low portion a first predetermined number of bits, and the high portion a second predetermined number of bits and producing a keystream output value by a logical exclusive-OR operation on rotated high and low portions.

6. The computer usable medium/memory of claim 5 wherein the low portion is rotated 3 bits to the left, and the high portion is rotated 3 bits to the right.