Method and apparatus for improving engineering change order placement in integrated circuit designs

• US 6,014,506 A
• Filed: 03/21/1996
• Issued: 01/11/2000
• Est. Priority Date: 10/31/1995
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Thumma, Bala, Ashtaputre, Sunil, Hossain, Moazzem
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/621,742
• Time in Patent Office: 1,391 Days
• Field of Search: 364/488-491
• US Class Current: 716/104
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (A) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (B) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (C) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (a) modifying the netlist pursuant to an engineering change order (ECO); and (b) making an ECO placement of at least one cell into the layout area by (i) picking an unplaced cell from a set of unplaced cells to be a picked cell; (ii) determining a target window within said layout area for the placement of said picked cell; (iii) mapping said picked cell inside said target window; (iv) removing said picked cell from said set of unplaced cells; (v) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to other cells, and modifying said placement of said picked cell if it improves timing; and (vi) repeating steps (i)-(v) until said set of unplaced cells is empty. A layout tool implements the method on a computer system to form a portion of an integrated circuit fabrication system.

Claims

1. A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool, said method comprising:

placing cells specified by said netlist in a layout area in a placement step, said cells including pins that are interconnected by nets;

verifying timing constraints in a timing verification step of said placed cells in said layout area; and

if said timing verification step indicates that timing does not verify in that said timing constraints are not met;

modifying said netlist pursuant to an engineering change order (ECO); and

making an ECO placement of at least one cell into said layout area by;

(1) picking an unplaced cell from a set of unplaced cells to be a picked cell;

(2) determining a target window within said layout area for the placement of said picked cell;

(3) mapping said picked cell inside said target window;

(4) removing said picked cell from said set of unplaced cells;

(5) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to said placed cells, and modifying said placement of said picked cell with respect to said placed cells if modifying said placement of said picked cell improves timing; and

(6) repeating steps (1)-(5) until said set of unplaced cells is empty wherein said optimizing the placement of said picked cell includes performing an m-way interchange;

wherein said m-way interchange includes;

determining a closed loop pattern of m windows;

moving cells either clockwise or counter-clockwise within said closed loop pattern;

calculating said target window for said picked cell;

picking an additional cell and calculating a target window for said additional cell until a predetermined number of additional cells has been picked;

picking a last additional cell and calculating a target window for said last additional cell such that said picked cell is within said target window for said last additional cell; and

,

moving said picked cell, said additional cells, and said last additional cell either clockwise or counter clockwise within said closed loop pattern; and

moving cells either clockwise or counter clockwise within said closed loop pattern.

2. A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool, said method comprising the steps of:

(A) placing cells specified by said netlist in a layout area in a placement step, said cells including pins that are interconnected by nets;

(B) verifying timing constraints in a timing verification step of said placed cells in said layout area; and

(C) if said timing verification step indicates that timing does not verify in that said timing constraints are not met;

(a) modifying said netlist pursuant to an engineering change order (ECO); and

(b) making an ECO placement of at least one cell into said layout area by;

(1) picking an unplaced cell from a set of unplaced cells to be a picked cell;

(2) determining a target window within said layout area for the placement of said picked cell;

(3) mapping said picked cell inside said target window;

(4) removing said picked cell from said set of unplaced cells;

(5) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to said placed cells, and modifying said placement of said picked cell with respect to said placed cells if modifying said placement of said picked cell improves timing; and

(6) repeating steps (1)-(5) until said set of unplaced cells is empty.

3. A method as recited in claim 2 wherein said step of determining said target window involves determining a minimum bounding box that encloses pins connected by nets of cells within the set of unplaced cells.

4. A method as recited in claim 3 wherein said step of determining said target window further involves using weights assigned said nets of said set of unplaced cells, said weights being related to timing constraints of said integrated circuit design.

5. A method as recited in claim 4 wherein said mapping step for a gate array includes the steps of:

mapping said cell to an empty site in said target window, if one exists; and

if no empty site exists in said target window, mapping said cell to a site in said window that would exhibit a minimum of overlap with adjacent cells, and moving any overlapped adjacent cells locally within the layout area until the overlap has been eliminated.

6. A method as recited in claim 4 wherein said mapping step for a standard cell includes the steps of:

mapping said cell to a row of cells within said window;

pushing any cells in that row to remove any overlap; and

if said row no longer fits within the target window, removing a cell from said row and placing it in another row.

7. A method as recited in claim 2 wherein said step of optimizing the placement of said picked cell includes at least one of an m-way interchange, a move pass, and a flip pass, wherein:

said m-way interchange includes determining a closed loop pattern of m windows, and moving cells either clockwise or counter clockwise within said closed loop pattern;

said move pass includes moving said picked cell into an available target window other than said target window; and

said flip pass includes re-orienting said picked cell within said target window.

8. A method as recited in claim 7 wherein said step of optimizing includes two or more of said m-way interchange, said move pass, and said flip pass.

9. A method as recited in claim 8 wherein said step of optimizing includes:

(a) performing an m-way interchange, a move pass, and a flip pass;

(b) performing a timing verification;

(c) determining the amount of timing improvement due to step (a); and

(d) repeating steps (a)-(c) if the timing improvement is greater than a predetermined value.

10. A method as described in claims 7, wherein said m-way interchange includes the steps of:

(a) calculating said target window for said picked cell;

(b) picking an additional cell and calculating a target window for said additional cell until a predetermined number of additional cells has been picked;

(c) picking a last additional cell and calculating a target window for said last additional cell such that said picked cell is within said target window for said last additional cell; and

,

(d) moving said picked cell, said additional cells, and said last additional cell either clockwise or counter clockwise within said closed loop pattern.

11. A method as described in claim 7, wherein said move pass includes the step of determining whether there is any space available in said available target window.

12. A method as described in claim 7, wherein said flip pass includes the steps of:

(a) determining a net length for said picked cell;

(b) picking a new orientation for said picked cell;

(c) determining a revised net length for said picked cell in said new orientation;

(d) determining whether said revised net length is less than said net length, wherein when said revised net length is not less than said net length, a determination is made as to whether any new additional orientations for said picked cell exist, wherein if said new additional orientations exist, picking said new orientation from said new additional orientations for said picked cell;

(e) repeating steps (c) and (d) until it is determined that said revised net length is less than said net length, wherein if it is determined that said revised net length is less than said net length, said picked cell to is moved to said new orientation.

13. A method for laying out an integrated circuit comprising the steps of:

picking a cell from a set of cells to be a picked cell;

determining a target window within said layout area for the placement of said picked cell;

mapping said picked cell inside said target window;

optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to other cells, and modifying said placement of said picked cell if it improves timing and reduces total net length; and

repeating the preceding steps until no further improvement is desired;

wherein said step of optimizing the placement of said picked cell includes at least one of an m-way interchange, a move pass, and a flip pass, wherein;

said m-way interchange includes determining a closed loop pattern of m windows, and moving cells either clockwise or counter clockwise within said closed loop pattern;

said move pass includes moving said picked cell into an available target window other than said target window; and

said flip pass includes re-orienting said picked cell within said target window.

14. A method for laying out an integrated circuit as recited in claim 13 wherein said step of optimizing includes two or more of said m-way interchange, said move pass, and said flip pass.

15. A method for laying out an integrated circuit as recited in claim 14 wherein said step of optimizing includes:

(a) performing an m-way interchange, a move pass, and a flip pass;

(b) performing a timing verification;

(c) determining the amount of timing improvement due to step (a); and

(d) repeating steps (a)-(c) if the timing improvement is greater than a predetermined value.

16. A method as described in claim 13, wherein said m-way interchange includes the steps of:

(a) calculating said target window for said picked cell;

(b) picking an additional cell and calculating a target window for said additional cell until a predetermined number of additional cells has been picked;

(c) picking a last additional cell and calculating a target window for said last additional cell such that said picked cell is within said target window for said last additional cell; and

,

(d) moving said picked cell, said additional cells, and said last additional cell either clockwise or counter clockwise within said closed loop pattern.

17. A method as described in claim 13, wherein said move pass includes the step of determining whether there is any space available in said available target window.

18. A method as described in claim 13, wherein said flip pass includes the steps of:

(a) determining a net length for said picked cell;

(b) picking a new orientation for said picked cell;

(c) determining a revised net length for said picked cell in said new orientation;

(d) determining whether said revised net length is less than said net length, wherein when said revised net length is not less than said net length, a determination is made as to whether any new additional orientations for said picked cell exist, wherein if said new additional orientations exist, picking said new orientation from said new additional orientations for said picked cell;

(e) repeating steps (c) and (d) until it is determined that said revised net length is less than said net length, wherein if it is determined that said revised net length is less than said net length, said picked cell to is moved to said new orientation.

19. An integrated circuit layout tool comprising:

a computer system including a central processing unit (CPU) and memory coupled to said CPU;

means for obtaining a netlist describing an integrated circuit design;

means for placing cells specified by said netlist in a layout area of said integrated circuit design, said cells including pins that are interconnected by nets;

means for verifying timing constraints of said placed cells in said layout area and if said timing constraints are not verified by said means for verifying timing constraints of said placed cells, then;

(a) means for modifying said netlist pursuant to an engineering change order (ECO); and

(b) means for making an ECO placement of at least one cell into said layout area based upon said timing constraints while adjusting any affected nets as specified by said netlist, wherein said means for making an ECO placement includes

(i) means for picking an unplaced cell from a set of unplaced cells to be a picked cell, and

(ii) means for optimizing the placement of said picked cell by analyzing said picked cell with respect to other cells, and modifying said placement of said picked cell if modifying said placement of said picked cell improves timing;

wherein said means for making an ECO placement further comprises;

means for determining a target window within said layout area for the placement of said picked cell;

means for mapping said picked cell inside said target window; and

means for removing said picked cell from said set of unplaced cells.

20. An integrated circuit layout tool as recited in claim 19 wherein said means for determining said target window utilizes a minimum bounding box that encloses said pins connected by nets of cells within the set of unplaced cells.

21. An integrated circuit layout tool as recited in claim 20 wherein said means for determining said target window further utilizes weights assigned to said nets of said set of unplaced cells, said weights being related to timing constraints of said integrated circuit design.

22. An integrated circuit layout tool as recited in claim 21 further including means for mapping for a gate array, wherein said means for mapping for a gate array includes:

means for mapping said picked cell to an empty site in said target window, if one exists and, if not, means for mapping said picked cell to a site in said window that would exhibit a minimum of overlap with adjacent cells, and means for moving any overlapped adjacent cells locally within the layout area until the overlap has been eliminated.

23. An integrated circuit layout tool as recited in claim 21 wherein said means for mapping for said picked cell includes:

means for mapping said picked cell to a row of cells within said target window;

means for pushing any cells in that row to remove any overlap; and

if said row no longer fits within the target window, means for removing a particular cell from said row and placing it in another row.

24. An integrated circuit layout tool as recited in claim 19 wherein said means for optimizing the placement of said picked cell utilizes at least one of an m-way interchange, a move pass, and a flip pass, wherein:

said m-way interchange includes determining a closed loop pattern of m windows, and moving cells either clockwise or counter clockwise within said closed loop pattern;

said move pass includes moving said picked cell into an available target window other than said target window; and

said flip pass includes re-orienting said picked cell within said target window.

27. An integrated circuit layout tool as described in claim 24, wherein said means for m-way interchange includes:

(a) means for calculating said target window for said picked cell;

(b) means for picking an additional cell and calculating a target window for said additional cell until a predetermined number of additional cells have been picked;

(c) means for picking a last additional cell and calculating a target window for said last additional cell such that said picked cell is within said target window for said last additional cell; and

, (d) means for moving said picked cell, said additional cells, and said last additional cell either clockwise or counter clockwise within said closed loop pattern.

28. An integrated circuit layout tool as described in claim 24, wherein said means for move pass includes means for determining whether there is any space available in said available target window.

29. An integrated circuit layout tool as described in claim 24, wherein said means for flip pass includes:

(a) means for determining a net length for said picked cell;

(b) means for picking a new orientation for said picked cell;

(c) means for determining a revised net length for said picked cell in said new orientation;

(d) means for determining whether said revised net length is less than said net length, wherein when said revised net length is not less than said net length, a determination is made as to whether any new additional orientations for said picked cell exist, wherein if said new additional orientations exist, picking said new orientation from said new additional orientations for said picked cell; and

(e) means for moving said picked cell to said new orientation when it is determined that said revised net length is less than said net length.

25. An integrated circuit layout tool as recited in claim 25 wherein said means for optimizing utilizes two or more of said m-way interchange, said move pass, and said flip pass.

26. An integrated circuit layout tool as recited in claim 25 wherein said means for optimizing includes:

(a) means for performing an m-way interchange, a move pass, and a flip pass;

(b) means for performing a timing verification; and

(c) means for determining the amount of timing improvement due to performing said m-way interchange, said move pass, and said flip pass.