Data processing circuit with self-timed instruction execution and power regulation

• US 6,014,749 A
• Filed: 11/12/1997
• Issued: 01/11/2000
• Est. Priority Date: 11/15/1996
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Baumann, Daniel, Gloor, Daniel, Gradenwitz, Paul G. M., Stegmann, Gerhard
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): EL HADY, NABIL M
• Application Number:
  US08/968,374
• Time in Patent Office: 790 Days
• Field of Search: 395/553, 395/559, 395/750.04, 326/93, 326/21, 375/359, 713/300, 713/320, 713/322, 713/340, 713/600, 714/814, 714/815, 710/25
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages

Abstract

The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Claims

1. A data processing circuit, comprising

a self-timed instruction execution unit having an interface for transmitting a first ready signal and for receiving a first request signal, the instruction execution unit generating the first ready signal to indicate readiness to start executing a first instruction of a plurality of instructions, which plurality of instructions have varying execution times, the instruction execution unit starting execution of the first instruction upon receiving the first request signal;

a sequencing unit coupled to the interface, for generating the first request signal in response to the first ready signal;

a timer for timing a predetermined time-interval starting with the execution of a second instruction whose execution precedes execution of the first instruction, the timer being coupled to the sequencing unit for disabling transmission of the first request signal to the instruction execution unit until after the time-interval has elapsed.

2. A data processing circuit according to claim 1, wherein the sequencing unit generates a predetermined first number of further request signals to the instruction execution unit upon receiving corresponding further ready signals, the further ready signals being generated by the execution unit upon completion of intermediate instructions executed between a start of execution of the second instruction and generating the request signal for starting execution of the first instruction, the sequencing unit comprising a counter for counting a second number of ready signals for completed intermediate instructions that the instruction execution unit starts executing after the second instruction, the counter being coupled to the sequencing unit for disabling said transmission of the first request signal when said second number has reached said predetermined first number.

3. A data processing circuit according to claim 2, wherein said second instruction and said predetermined first number are programmable.

4. A data processing circuit according to claim 1, comprising

a measuring circuit which measures a delay between transmission of the first ready signal and transmission of the first request signal for executing said first instruction,

a voltage regulator which controls a supply voltage applied to the instruction execution unit, a speed of execution of instructions depending on the supply voltage, said measuring circuit being coupled to a control input of the voltage regulator for regulating the delay towards a predetermined value.

5. A data processing circuit according to claim 1, comprising

a detection circuit which detects an excess time when the time-interval finishes before transmission of the ready signal,

a voltage regulator, for controlling a supply voltage applied to the instruction execution unit, a speed of execution of instructions depending on the supply voltage, the means for detecting being coupled to a control input of the voltage regulator for regulating away the excess time.

6. A data processing circuit according to claim 4, comprising means for detecting an excess time when the time interval finishes before transmission of the ready signal, the voltage regulator regulating the delay towards the predetermined value under control of the delay when the delay is greater than zero and under control of the excess time when the excess time is greater than zero.

7. A data processing circuit according to claim 2, comprising

a measuring circuit which measures a delay between transmission of the first ready signal and transmission of the first request signal for executing said first instruction,

a voltage regulator which controls a supply voltage applied to the instruction execution unit, a speed of execution of instructions depending on the supply voltage, said measuring circuit being coupled to a control input of the voltage regulator for regulating the delay towards a predetermined value.

8. A data processing circuit according to claim 2, comprising

a detection circuit which detects an excess time when the time-interval finishes before transmission of the ready signal,

a voltage regulator, for controlling a supply voltage applied to the instruction execution unit, a speed of execution of instructions depending on the supply voltage, the detection circuit being coupled to a control input of the voltage regulator for regulating away the excess time.

9. A data processing circuit, comprising

a self timed instruction execution unit having an interface for transmitting a ready signal and for receiving a request signal, the instruction execution unit generating the ready signal to indicate readiness to start executing a first instruction, the instruction execution unit starting execution of the first instruction upon receiving the request signal;

a sequencing unit coupled to the interface, for generating the request signal in response to the ready signal, said sequencing unit generates a predetermined first number of further request signals and transmits said further request signals to the instruction execution unit upon receiving corresponding further ready signals to execute a corresponding predetermined number of intermediate instructions between a start of execution of the second instruction, whose execution precedes execution of the first instruction, and generating the request signal for starting execution of the first instruction;

a timer for timing a predetermined time-interval starting with the execution of a second instruction and generating the request signal for starting execution of the first instruction, the timer being coupled to the sequencing unit for disabling transmission of the request signal to the instruction execution unit for starting execution of the first instruction until after the time-interval has elapsed;

a counter coupled to the sequencing unit for counting a second number of intermediate instructions that the instruction execution unit starts executing after the second instruction, wherein the counter disables said transmission of said further request signals to the execution unit to execute said intermediate instructions when said second number has reached the predetermined first number.