Method of managing defects in flash disk memories

• US 6,014,755 A
• Filed: 08/12/1996
• Issued: 01/11/2000
• Est. Priority Date: 10/30/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wells, Steven E., Magnusson, Eric J., Hasbun, Robert N.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/700,676
• Time in Patent Office: 1,247 Days
• Field of Search: 395/182.06, 365/218, 714/8, 714/5, 714/29, 714/42, 714/54, 714/710, 714/718, 714/769
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

Claims

1. A method for erase defect management in a memory comprising a plurality of memory arrays divided into individually erasable blocks of memory, said method comprising:

a) executing an erase operation with a high erase voltage on a block of memory in a memory array;

b) determining if an error occurred for the erase operation;

c) determining if the high erase voltage is low;

d) disabling write operations to the memory array, if the high erase voltage is low; and

e) executing read operations to the memory array, if requested.

2. The method of claim 1 wherein the memory comprises flash electrically erasable programmable read only memory (EEPROM) memory cells.

3. The method of claim 1 wherein executing an erase operation further comprises:

i) writing logical ones to the block.

4. The method of claim 1 wherein determining if an error occurred further comprises:

i) comparing data stored in the block with logical ones.

5. The method of claim 4 wherein comparing data stored in the block with logical ones further comprises reading data stored in the block.

6. The method of claim 1 further comprising:

f) marking a sector of the block being erased bad, if an erase error occurred and the high erase voltage is not low.